Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

Further changes still need to be made to the XC code.

arch/alpha/ev5.cc:
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
base/remote_gdb.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
kern/kernel_stats.cc:
sim/pseudo_inst.cc:
    Hand merge.

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e

2 files changed, 99 insertions, 91 deletions

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 51d679a63..38b43fef5 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -44,6 +44,7 @@
 #include "base/stats/events.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
+#include "cpu/cpu_exec_context.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/profile.hh"
@@ -94,7 +95,7 @@ SimpleCPU::init()
         ExecContext *xc = execContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(&xc->regs, xc->cpu_id);
+        TheISA::initCPU(xc, xc->readCpuId());
     }
 #endif
 }
@@ -132,22 +133,24 @@ SimpleCPU::CacheCompletionEvent::description()
 }
 
 SimpleCPU::SimpleCPU(Params *p)
-    : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
+    : BaseCPU(p), tickEvent(this, p->width), cpuXC(NULL),
       cacheCompletionEvent(this)
 {
     _status = Idle;
 #if FULL_SYSTEM
-    xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
+    cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
 #else
-    xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
+    cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
+                               /* asid */ 0);
 #endif // !FULL_SYSTEM
+    xcProxy = cpuXC->getProxy();
 
     icacheInterface = p->icache_interface;
     dcacheInterface = p->dcache_interface;
 
     memReq = new MemReq();
-    memReq->xc = xc;
+    memReq->xc = xcProxy;
     memReq->asid = 0;
     memReq->data = new uint8_t[64];
 
@@ -158,7 +161,7 @@ SimpleCPU::SimpleCPU(Params *p)
     lastIcacheStall = 0;
     lastDcacheStall = 0;
 
-    execContexts.push_back(xc);
+    execContexts.push_back(xcProxy);
 }
 
 SimpleCPU::~SimpleCPU()
@@ -207,7 +210,7 @@ void
 SimpleCPU::activateContext(int thread_num, int delay)
 {
     assert(thread_num == 0);
-    assert(xc);
+    assert(cpuXC);
 
     assert(_status == Idle);
     notIdleFraction++;
@@ -220,7 +223,7 @@ void
 SimpleCPU::suspendContext(int thread_num)
 {
     assert(thread_num == 0);
-    assert(xc);
+    assert(cpuXC);
 
     assert(_status == Running);
     notIdleFraction--;
@@ -301,7 +304,7 @@ SimpleCPU::serialize(ostream &os)
     SERIALIZE_ENUM(_status);
     SERIALIZE_SCALAR(inst);
     nameOut(os, csprintf("%s.xc", name()));
-    xc->serialize(os);
+    cpuXC->serialize(os);
     nameOut(os, csprintf("%s.tickEvent", name()));
     tickEvent.serialize(os);
     nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
@@ -314,7 +317,7 @@ SimpleCPU::unserialize(Checkpoint *cp, const string &section)
     BaseCPU::unserialize(cp, section);
     UNSERIALIZE_ENUM(_status);
     UNSERIALIZE_SCALAR(inst);
-    xc->unserialize(cp, csprintf("%s.xc", section));
+    cpuXC->unserialize(cp, csprintf("%s.xc", section));
     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
     cacheCompletionEvent
         .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
@@ -345,16 +348,16 @@ SimpleCPU::copySrcTranslate(Addr src)
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(memReq);
+    Fault fault = cpuXC->translateDataReadReq(memReq);
 
     if (fault == NoFault) {
-        xc->copySrcAddr = src;
-        xc->copySrcPhysAddr = memReq->paddr + offset;
+        cpuXC->copySrcAddr = src;
+        cpuXC->copySrcPhysAddr = memReq->paddr + offset;
     } else {
         assert(!fault->isAlignmentFault());
 
-        xc->copySrcAddr = 0;
-        xc->copySrcPhysAddr = 0;
+        cpuXC->copySrcAddr = 0;
+        cpuXC->copySrcPhysAddr = 0;
     }
     return fault;
 }
@@ -367,7 +370,7 @@ SimpleCPU::copy(Addr dest)
     // Only support block sizes of 64 atm.
     assert(blk_size == 64);
     uint8_t data[blk_size];
-    //assert(xc->copySrcAddr);
+    //assert(cpuXC->copySrcAddr);
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
@@ -380,19 +383,19 @@ SimpleCPU::copy(Addr dest)
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(memReq);
+    Fault fault = cpuXC->translateDataWriteReq(memReq);
 
     if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
         // Need to read straight from memory since we have more than 8 bytes.
-        memReq->paddr = xc->copySrcPhysAddr;
-        xc->mem->read(memReq, data);
+        memReq->paddr = cpuXC->copySrcPhysAddr;
+        cpuXC->mem->read(memReq, data);
         memReq->paddr = dest_addr;
-        xc->mem->write(memReq, data);
+        cpuXC->mem->write(memReq, data);
         if (dcacheInterface) {
             memReq->cmd = Copy;
             memReq->completionEvent = NULL;
-            memReq->paddr = xc->copySrcPhysAddr;
+            memReq->paddr = cpuXC->copySrcPhysAddr;
             memReq->dest = dest_addr;
             memReq->size = 64;
             memReq->time = curTick;
@@ -412,7 +415,7 @@ Fault
 SimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
-        Fault fault = xc->read(memReq,data);
+        Fault fault = cpuXC->read(memReq,data);
 
         if (traceData) {
             traceData->setAddr(addr);
@@ -423,7 +426,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(memReq);
+    Fault fault = cpuXC->translateDataReadReq(memReq);
 
     // if we have a cache, do cache access too
     if (fault == NoFault && dcacheInterface) {
@@ -443,12 +446,12 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
             _status = DcacheMissStall;
         } else {
             // do functional access
-            fault = xc->read(memReq, data);
+            fault = cpuXC->read(memReq, data);
 
         }
     } else if(fault == NoFault) {
         // do functional access
-        fault = xc->read(memReq, data);
+        fault = cpuXC->read(memReq, data);
 
     }
 
@@ -508,11 +511,11 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(memReq);
+    Fault fault = cpuXC->translateDataWriteReq(memReq);
 
     // do functional access
     if (fault == NoFault)
-        fault = xc->write(memReq, data);
+        fault = cpuXC->write(memReq, data);
 
     if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Write;
@@ -589,7 +592,7 @@ SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 Addr
 SimpleCPU::dbg_vtophys(Addr addr)
 {
-    return vtophys(xc, addr);
+    return vtophys(xcProxy, addr);
 }
 #endif // FULL_SYSTEM
 
@@ -637,9 +640,9 @@ SimpleCPU::post_interrupt(int int_num, int index)
 {
     BaseCPU::post_interrupt(int_num, index);
 
-    if (xc->status() == ExecContext::Suspended) {
+    if (cpuXC->status() == ExecContext::Suspended) {
                 DPRINTF(IPI,"Suspended Processor awoke\n");
-        xc->activate();
+        cpuXC->activate();
     }
 }
 #endif // FULL_SYSTEM
@@ -655,16 +658,16 @@ SimpleCPU::tick()
     Fault fault = NoFault;
 
 #if FULL_SYSTEM
-    if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
+    if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() &&
         status() != IcacheMissComplete) {
         int ipl = 0;
         int summary = 0;
         checkInterrupts = false;
 
-        if (xc->readMiscReg(IPR_SIRR)) {
+        if (cpuXC->readMiscReg(IPR_SIRR)) {
             for (int i = INTLEVEL_SOFTWARE_MIN;
                  i < INTLEVEL_SOFTWARE_MAX; i++) {
-                if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
                     ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                     summary |= (ULL(1) << i);
@@ -672,7 +675,7 @@ SimpleCPU::tick()
             }
         }
 
-        uint64_t interrupts = xc->cpu->intr_status();
+        uint64_t interrupts = cpuXC->cpu->intr_status();
         for (int i = INTLEVEL_EXTERNAL_MIN;
             i < INTLEVEL_EXTERNAL_MAX; i++) {
             if (interrupts & (ULL(1) << i)) {
@@ -682,24 +685,25 @@ SimpleCPU::tick()
             }
         }
 
-        if (xc->readMiscReg(IPR_ASTRR))
+        if (cpuXC->readMiscReg(IPR_ASTRR))
             panic("asynchronous traps not implemented\n");
 
-        if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
-            xc->setMiscReg(IPR_ISR, summary);
-            xc->setMiscReg(IPR_INTID, ipl);
-            Fault(new InterruptFault)->invoke(xc);
+        if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
+            cpuXC->setMiscReg(IPR_ISR, summary);
+            cpuXC->setMiscReg(IPR_INTID, ipl);
+
+            Fault(new InterruptFault)->invoke(xcProxy);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                    xc->readMiscReg(IPR_IPLR), ipl, summary);
+                    cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
         }
     }
 #endif
 
     // maintain $r0 semantics
-    xc->regs.intRegFile[ZeroReg] = 0;
+    cpuXC->setIntReg(ZeroReg, 0);
 #ifdef TARGET_ALPHA
-    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
+    cpuXC->setFloatRegDouble(ZeroReg, 0.0);
 #endif // TARGET_ALPHA
 
     if (status() == IcacheMissComplete) {
@@ -721,13 +725,13 @@ SimpleCPU::tick()
 #endif
 
         memReq->cmd = Read;
-        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
-                     IFETCH_FLAGS(xc->regs.pc));
+        memReq->reset(cpuXC->readPC() & ~3, sizeof(uint32_t),
+                     IFETCH_FLAGS(cpuXC->readPC()));
 
-        fault = xc->translateInstReq(memReq);
+        fault = cpuXC->translateInstReq(memReq);
 
         if (fault == NoFault)
-            fault = xc->mem->read(memReq, inst);
+            fault = cpuXC->mem->read(memReq, inst);
 
         if (icacheInterface && fault == NoFault) {
             memReq->completionEvent = NULL;
@@ -764,29 +768,30 @@ SimpleCPU::tick()
         inst = gtoh(inst);
         curStaticInst = StaticInst::decode(makeExtMI(inst, xc->readPC()));
 
-        traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
-                                         xc->regs.pc);
+        traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
+                                         cpuXC->readPC());
 
 #if FULL_SYSTEM
-        xc->setInst(inst);
+        cpuXC->setInst(inst);
 #endif // FULL_SYSTEM
 
-        xc->func_exe_inst++;
+        cpuXC->func_exe_inst++;
 
         fault = curStaticInst->execute(this, traceData);
 
 #if FULL_SYSTEM
-        if (xc->fnbin) {
-            assert(xc->kernelStats);
-            system->kernelBinning->execute(xc, inst);
+        if (system->kernelBinning->fnbin) {
+            assert(kernelStats);
+            system->kernelBinning->execute(xcProxy, inst);
         }
 
-        if (xc->profile) {
-            bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
-            xc->profilePC = usermode ? 1 : xc->regs.pc;
-            ProfileNode *node = xc->profile->consume(xc, inst);
+        if (cpuXC->profile) {
+            bool usermode =
+                (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+            cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
+            ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
             if (node)
-                xc->profileNode = node;
+                cpuXC->profileNode = node;
         }
 #endif
 
@@ -806,29 +811,29 @@ SimpleCPU::tick()
             traceData->finalize();
         }
 
-        traceFunctions(xc->regs.pc);
+        traceFunctions(cpuXC->readPC());
 
     }	// if (fault == NoFault)
 
     if (fault != NoFault) {
 #if FULL_SYSTEM
-        fault->invoke(xc);
+        fault->invoke(xcProxy);
 #else // !FULL_SYSTEM
-        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
+        fatal("fault (%d) detected @ PC 0x%08p", fault, cpuXC->readPC());
 #endif // FULL_SYSTEM
     }
     else {
         // go to the next instruction
-        xc->regs.pc = xc->regs.npc;
-        xc->regs.npc += sizeof(MachInst);
+        cpuXC->setPC(cpuXC->readNextPC());
+        cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
     }
 
 #if FULL_SYSTEM
     Addr oldpc;
     do {
-        oldpc = xc->regs.pc;
-        system->pcEventQueue.service(xc);
-    } while (oldpc != xc->regs.pc);
+        oldpc = cpuXC->readPC();
+        system->pcEventQueue.service(xcProxy);
+    } while (oldpc != cpuXC->readPC());
 #endif
 
     assert(status() == Running ||
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 0b8d84e53..4ab9a1c3e 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -32,7 +32,7 @@
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/cpu_exec_context.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/sampler/sampler.hh"
 #include "cpu/static_inst.hh"
@@ -54,6 +54,7 @@ class Process;
 
 #endif // FULL_SYSTEM
 
+class ExecContext;
 class MemInterface;
 class Checkpoint;
 
@@ -148,7 +149,9 @@ class SimpleCPU : public BaseCPU
 
   public:
     // execution context
-    ExecContext *xc;
+    CPUExecContext *cpuXC;
+
+    ExecContext *xcProxy;
 
     void switchOut(Sampler *s);
     void takeOverFrom(BaseCPU *oldCPU);
@@ -275,86 +278,86 @@ class SimpleCPU : public BaseCPU
 
     uint64_t readIntReg(const StaticInst *si, int idx)
     {
-        return xc->readIntReg(si->srcRegIdx(idx));
+        return cpuXC->readIntReg(si->srcRegIdx(idx));
     }
 
     float readFloatRegSingle(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return xc->readFloatRegSingle(reg_idx);
+        return cpuXC->readFloatRegSingle(reg_idx);
     }
 
     double readFloatRegDouble(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return xc->readFloatRegDouble(reg_idx);
+        return cpuXC->readFloatRegDouble(reg_idx);
     }
 
     uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return xc->readFloatRegInt(reg_idx);
+        return cpuXC->readFloatRegInt(reg_idx);
     }
 
     void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
-        xc->setIntReg(si->destRegIdx(idx), val);
+        cpuXC->setIntReg(si->destRegIdx(idx), val);
     }
 
     void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        xc->setFloatRegSingle(reg_idx, val);
+        cpuXC->setFloatRegSingle(reg_idx, val);
     }
 
     void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        xc->setFloatRegDouble(reg_idx, val);
+        cpuXC->setFloatRegDouble(reg_idx, val);
     }
 
     void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        xc->setFloatRegInt(reg_idx, val);
+        cpuXC->setFloatRegInt(reg_idx, val);
     }
 
-    uint64_t readPC() { return xc->readPC(); }
-    void setNextPC(uint64_t val) { xc->setNextPC(val); }
+    uint64_t readPC() { return cpuXC->readPC(); }
+    void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
 
     MiscReg readMiscReg(int misc_reg)
     {
-        return xc->readMiscReg(misc_reg);
+        return cpuXC->readMiscReg(misc_reg);
     }
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return xc->readMiscRegWithEffect(misc_reg, fault);
+        return cpuXC->readMiscRegWithEffect(misc_reg, fault);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return xc->setMiscReg(misc_reg, val);
+        return cpuXC->setMiscReg(misc_reg, val);
     }
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return xc->setMiscRegWithEffect(misc_reg, val);
+        return cpuXC->setMiscRegWithEffect(misc_reg, val);
     }
 
 #if FULL_SYSTEM
-    Fault hwrei() { return xc->hwrei(); }
-    int readIntrFlag() { return xc->readIntrFlag(); }
-    void setIntrFlag(int val) { xc->setIntrFlag(val); }
-    bool inPalMode() { return xc->inPalMode(); }
-    void trap(Fault fault) { fault->invoke(xc); }
-    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
+    Fault hwrei() { return cpuXC->hwrei(); }
+    int readIntrFlag() { return cpuXC->readIntrFlag(); }
+    void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
+    bool inPalMode() { return cpuXC->inPalMode(); }
+    void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+    bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
 #else
-    void syscall() { xc->syscall(); }
+    void syscall() { cpuXC->syscall(); }
 #endif
 
-    bool misspeculating() { return xc->misspeculating(); }
-    ExecContext *xcBase() { return xc; }
+    bool misspeculating() { return cpuXC->misspeculating(); }
+    ExecContext *xcBase() { return xcProxy; }
 };
 
 #endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__