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| author | Ron Dreslinski <rdreslin@umich.edu> | 2005-12-01 18:47:36 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2005-12-01 18:47:36 -0500 |
| commit | ffc32970f63ae1330f080a7ea14a79bc4446bc33 (patch) | |
| tree | 39f617be8ba2d16fc183c1c09ffa294ce0a81e4c /cpu/simple | |
| parent | 481219caf6f4bdb79311ec4592a061b76ecad503 (diff) | |
| download | gem5-ffc32970f63ae1330f080a7ea14a79bc4446bc33.tar.xz | |
Two small fixes for mem_req's and Probe path with MOSI/MOESI
cpu/simple/cpu.cc:
Properly set the Instruction Read bit in the Memory Request
--HG--
extra : convert_revision : e1a4756f32718fd8ef3ac3db16625bd6d8f07cc5
Diffstat (limited to 'cpu/simple')
| -rw-r--r-- | cpu/simple/cpu.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index d352d8c03..a7f4fa499 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -382,6 +382,7 @@ SimpleCPU::copy(Addr dest) memReq->dest = dest_addr; memReq->size = 64; memReq->time = curTick; + memReq->flags &= ~INST_READ; dcacheInterface->access(memReq); } } @@ -412,6 +413,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; + memReq->flags &= ~INST_READ; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -500,6 +502,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; + memReq->flags &= ~INST_READ; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -714,6 +717,7 @@ SimpleCPU::tick() memReq->completionEvent = NULL; memReq->time = curTick; + memReq->flags |= INST_READ; MemAccessResult result = icacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is |