Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891

2 files changed, 27 insertions, 15 deletions

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 1f362876f..d826c589e 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -659,12 +659,11 @@ SimpleCPU::tick()
         int ipl = 0;
         int summary = 0;
         checkInterrupts = false;
-        IntReg *ipr = xc->regs.ipr;
 
-        if (xc->regs.ipr[IPR_SIRR]) {
+        if (xc->readMiscReg(IPR_SIRR)) {
             for (int i = INTLEVEL_SOFTWARE_MIN;
                  i < INTLEVEL_SOFTWARE_MAX; i++) {
-                if (ipr[IPR_SIRR] & (ULL(1) << i)) {
+                if (xc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
                     ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                     summary |= (ULL(1) << i);
@@ -682,16 +681,16 @@ SimpleCPU::tick()
             }
         }
 
-        if (ipr[IPR_ASTRR])
+        if (xc->readMiscReg(IPR_ASTRR))
             panic("asynchronous traps not implemented\n");
 
-        if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
-            ipr[IPR_ISR] = summary;
-            ipr[IPR_INTID] = ipl;
+        if (ipl && ipl > xc->readMiscReg(IPR_IPLR)) {
+            xc->setMiscReg(IPR_ISR, summary);
+            xc->setMiscReg(IPR_INTID, ipl);
             (new InterruptFault)->ev5_trap(xc);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                    ipr[IPR_IPLR], ipl, summary);
+                    xc->readMiscReg(IPR_IPLR), ipl, summary);
         }
     }
 #endif
@@ -782,7 +781,7 @@ SimpleCPU::tick()
         }
 
         if (xc->profile) {
-            bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
+            bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
             xc->profilePC = usermode ? 1 : xc->regs.pc;
             ProfileNode *node = xc->profile->consume(xc, inst);
             if (node)
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index c58b3c5ba..243172821 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU
 {
   protected:
     typedef TheISA::MachInst MachInst;
+    typedef TheISA::MiscReg MiscReg;
   public:
     // main simulation loop (one cycle)
     void tick();
@@ -321,15 +322,27 @@ class SimpleCPU : public BaseCPU
     uint64_t readPC() { return xc->readPC(); }
     void setNextPC(uint64_t val) { xc->setNextPC(val); }
 
-    uint64_t readUniq() { return xc->readUniq(); }
-    void setUniq(uint64_t val) { xc->setUniq(val); }
+    MiscReg readMiscReg(int misc_reg)
+    {
+        return xc->readMiscReg(misc_reg);
+    }
+
+    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    {
+        return xc->readMiscRegWithEffect(misc_reg, fault);
+    }
 
-    uint64_t readFpcr() { return xc->readFpcr(); }
-    void setFpcr(uint64_t val) { xc->setFpcr(val); }
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    {
+        return xc->setMiscReg(misc_reg, val);
+    }
+
+    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    {
+        return xc->setMiscRegWithEffect(misc_reg, val);
+    }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
-    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
     int readIntrFlag() { return xc->readIntrFlag(); }
     void setIntrFlag(int val) { xc->setIntrFlag(val); }