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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-24 08:52:38 -0500 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2006-02-24 08:52:38 -0500 |
| commit | 7a37037358ae5800d0f6a40130929669d836fe70 (patch) | |
| tree | 31b2c9f9033585b7c163319c8abcb80aa7bd26f4 /cpu/simple | |
| parent | f6cac25dcfbeed77642026deb81979f651104efe (diff) | |
| parent | 51647e7bec8e8607fc5713b4ace2c24ce8a7455a (diff) | |
| download | gem5-7a37037358ae5800d0f6a40130929669d836fe70.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch
arch/isa_parser.py:
SCCS merged
--HG--
extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
Diffstat (limited to 'cpu/simple')
| -rw-r--r-- | cpu/simple/cpu.cc | 17 | ||||
| -rw-r--r-- | cpu/simple/cpu.hh | 1 |
2 files changed, 16 insertions, 2 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index f7a6d2c21..944bdbb0a 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -84,6 +84,21 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) { } + +void +SimpleCPU::init() +{ + BaseCPU::init(); +#if FULL_SYSTEM + for (int i = 0; i < execContexts.size(); ++i) { + ExecContext *xc = execContexts[i]; + + // initialize CPU, including PC + TheISA::initCPU(&xc->regs, xc->cpu_id); + } +#endif +} + void SimpleCPU::TickEvent::process() { @@ -124,8 +139,6 @@ SimpleCPU::SimpleCPU(Params *p) #if FULL_SYSTEM xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); - // initialize CPU, including PC - initCPU(&xc->regs); #else xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); #endif // !FULL_SYSTEM diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index d3e0323b6..ed7b1e29b 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -68,6 +68,7 @@ class SimpleCPU : public BaseCPU public: // main simulation loop (one cycle) void tick(); + virtual void init(); private: struct TickEvent : public Event |