More progress... run a few instructions now, but die on the second

memory access (I think because we're deallocating our one and only
CpuRequest object).

base/loader/aout_object.cc:
base/loader/ecoff_object.cc:
base/loader/elf_object.cc:
    Add flag to force allocation of new pages on data writes.
cpu/simple/cpu.cc:
    Several minor fixes.
    Switch to atomic mode for now.
mem/physical.hh:
    Don't copy the packet to the response event, just keep a reference
    to the original.
mem/translating_port.cc:
mem/translating_port.hh:
    Add parameter to writeBlobFunctional() to force allocation of
    unallocated pages on writes.

--HG--
extra : convert_revision : 05cb31c7b0047b492dcfa0d12ddee690ef762b44

1 files changed, 7 insertions, 5 deletions

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 7da000a35..41acd2456 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -659,7 +659,7 @@ SimpleCPU::dbg_vtophys(Addr addr)
 void
 SimpleCPU::sendIcacheRequest()
 {
-#if 1
+#if 0
     bool success = icachePort.sendTiming(*pkt);
 
     unscheduleTickEvent();
@@ -674,7 +674,7 @@ SimpleCPU::sendIcacheRequest()
         _status = IcacheWaitResponse;
     }
 #else
-    Tick latency = icachePort.sendAtomic(pkt);
+    Tick latency = icachePort.sendAtomic(*pkt);
 
     unscheduleTickEvent();
     scheduleTickEvent(latency);
@@ -695,7 +695,7 @@ SimpleCPU::sendDcacheRequest()
 {
     unscheduleTickEvent();
 
-#if 1
+#if 0
     bool success = dcachePort.sendTiming(*pkt);
 
     lastDcacheStall = curTick;
@@ -706,7 +706,7 @@ SimpleCPU::sendDcacheRequest()
         _status = DcacheWaitResponse;
     }
 #else
-    Tick latency = dcachePort.sendAtomic(pkt);
+    Tick latency = dcachePort.sendAtomic(*pkt);
 
     scheduleTickEvent(latency);
 
@@ -891,7 +891,7 @@ SimpleCPU::tick()
 /*	memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
                      IFETCH_FLAGS(xc->regs.pc));
 */
-//NEED NEW TRANSLATION HERE
+
         fault = xc->translateInstReq(req);
 
         if (fault == No_Fault) {
@@ -900,8 +900,10 @@ SimpleCPU::tick()
             pkt->addr = req->paddr;
             pkt->size = sizeof(MachInst);
             pkt->req = req;
+            pkt->data = (uint8_t *)&inst;
 
             sendIcacheRequest();
+            return;
 /*	    fault = xc->mem->read(memReq, inst);
 
         if (icacheInterface && fault == No_Fault) {