More progress toward compiling... partly by

fixing things, partly by ignoring CPU models
that don't currently compile.

SConscript:
    Split sources for fast, simple, and o3 CPU models into
    separate source lists.  For now none of these are included
    in the base source list, so you won't get any CPU models
    at all... but we still can't compile the other stuff so
    it's not an issue.

    Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
    FunctionalMemory -> Memory
cpu/pc_event.hh:
    Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
    Move Port functions into .cc file.
mem/port.hh:
    Make recvAddressRangesQuery panic by default instead
    of being abstract... do CPUs need to implement this?
mem/request.hh:
    Add prefetch flags.
sim/syscall_emul.hh:
    Start to fix...

--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7

2 files changed, 38 insertions, 17 deletions

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 0760f978c..b6823fb63 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -102,17 +102,42 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
 {
 }
 
-void SimpleCPU::CacheCompletionEvent::process()
+
+bool
+SimpleCPU::CpuPort::recvTiming(Packet &pkt)
 {
-    cpu->processCacheCompletion();
+    cpu->processResponse(pkt);
+    return true;
 }
 
-const char *
-SimpleCPU::CacheCompletionEvent::description()
+Tick
+SimpleCPU::CpuPort::recvAtomic(Packet &pkt)
 {
-    return "SimpleCPU cache completion event";
+    panic("CPU doesn't expect callback!");
+    return curTick;
 }
 
+void
+SimpleCPU::CpuPort::recvFunctional(Packet &pkt)
+{
+    panic("CPU doesn't expect callback!");
+}
+
+void
+SimpleCPU::CpuPort::recvStatusChange(Status status)
+{
+    cpu->recvStatusChange(status);
+}
+
+Packet *
+SimpleCPU::CpuPort::recvRetry()
+{
+    return cpu->processRetry();
+}
+
+
+
+
 SimpleCPU::SimpleCPU(Params *p)
     : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
       cacheCompletionEvent(this), dcachePort(this), icachePort(this)
@@ -697,9 +722,9 @@ SimpleCPU::sendDcacheRequest()
 void
 SimpleCPU::processResponse(Packet *response)
 {
-    // For what things is the CPU the consumer of the packet it sent out?
-    // This may create a memory leak if that's the case and it's expected of the
-    // SimpleCPU to delete its own packet.
+    // For what things is the CPU the consumer of the packet it sent
+    // out?  This may create a memory leak if that's the case and it's
+    // expected of the SimpleCPU to delete its own packet.
     pkt = response;
 
     switch (status()) {
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 42fec55f1..3d445b001 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -79,19 +79,15 @@ class SimpleCPU : public BaseCPU
 
       protected:
 
-        virtual bool recvTiming(Packet &pkt)
-        { cpu->processCacheCompletion(pkt); return true; }
+        virtual bool recvTiming(Packet &pkt);
 
-        virtual Tick recvAtomic(Packet &pkt)
-        { panic("CPU doesn't expect callback!"); return curTick; }
+        virtual Tick recvAtomic(Packet &pkt);
 
-        virtual void recvFunctional(Packet &pkt)
-        { panic("CPU doesn't expect callback!"); }
+        virtual void recvFunctional(Packet &pkt);
 
-        virtual void recvStatusChange(Status status)
-        { cpu->recvStatusChange(status); }
+        virtual void recvStatusChange(Status status);
 
-        virtual Packet *recvRetry() { return cpu->processRetry(); }
+        virtual Packet *recvRetry();
     };
 
     CpuPort icachePort;