Some more useful debugging info for kernel panic and die events

Increase the default number of CSHR's, we should really fix this or make it a parameter

Use a setBlocked call to tell the bus it should block

New technique for sampling and switchover:
1) Sampler switchover event happens
2) All cpus in the current phase of sampling associated with this sampler are signaled to switchover
3) Each cpu drains it's pipe of things being executed (stops fetching and waits for empty pipe)
4) Once the pipe is empty the cpu calls back to the sampler to signal it has finished, and moves into the switchedout state (continues not to fetch)
5) The sampler collects all the signals, once all cpus are drained it calls the new cpu's in the next phase to takeover from the correct cpu
6) The statistics are reset and the next switchover time is calculated from this point

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Reconfigure the way the sampling switchover works
cpu/pc_event.cc:
    More debugging information on kernel panic's
kern/linux/linux_system.cc:
    More debug info for Kernel Die events
kern/linux/linux_system.hh:
    More debug info for kernel die events

--HG--
extra : convert_revision : 61cc42e43ba738705aa1f1d167b65d4d6dee51ae

1 files changed, 21 insertions, 6 deletions

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 9f4f821d4..2f1e8e1f1 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -47,6 +47,7 @@
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/full_cpu/smt.hh"
+#include "cpu/sampling_cpu/sampling_cpu.hh"
 #include "cpu/simple_cpu/simple_cpu.hh"
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
@@ -179,11 +180,21 @@ SimpleCPU::~SimpleCPU()
 }
 
 void
-SimpleCPU::switchOut()
+SimpleCPU::switchOut(SamplingCPU *s)
 {
-    _status = SwitchedOut;
-    if (tickEvent.scheduled())
-        tickEvent.squash();
+    sampler = s;
+    if (status() == DcacheMissStall) {
+        DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
+        _status = DcacheMissSwitch;
+    }
+    else {
+        _status = SwitchedOut;
+
+        if (tickEvent.scheduled())
+            tickEvent.squash();
+
+        sampler->signalSwitched();
+    }
 }
 
 
@@ -203,8 +214,6 @@ SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
             tickEvent.schedule(curTick);
         }
     }
-
-    oldCPU->switchOut();
 }
 
 
@@ -631,6 +640,12 @@ SimpleCPU::processCacheCompletion()
         _status = Running;
         scheduleTickEvent(1);
         break;
+      case DcacheMissSwitch:
+        if (memReq->cmd.isRead()) {
+            curStaticInst->execute(this,traceData);
+        }
+        _status = SwitchedOut;
+        sampler->signalSwitched();
       case SwitchedOut:
         // If this CPU has been switched out due to sampling/warm-up,
         // ignore any further status changes (e.g., due to cache