summaryrefslogtreecommitdiff
path: root/cpu/simple_cpu/simple_cpu.cc
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2004-11-18 00:24:36 -0500
committerNathan Binkert <binkertn@umich.edu>2004-11-18 00:24:36 -0500
commit44ef49bd2b66799add0077ecf60c2a111d9a2844 (patch)
tree5108d07ebea93a71d9c01d7742b21554fbe95610 /cpu/simple_cpu/simple_cpu.cc
parentaddf5436876ad7decb393abf76373e61a829b923 (diff)
downloadgem5-44ef49bd2b66799add0077ecf60c2a111d9a2844.tar.xz
undo simple CPU changes
--HG-- extra : convert_revision : dce0d9f7d34243899f699488c6534fb1ccea4849
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.cc')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc49
1 files changed, 12 insertions, 37 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 4bd7ce638..d48f93663 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -103,7 +103,7 @@ SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
void SimpleCPU::CacheCompletionEvent::process()
{
- cpu->processCacheCompletion(read);
+ cpu->processCacheCompletion();
}
const char *
@@ -414,25 +414,21 @@ template <class T>
Fault
SimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- Fault fault;
+ memReq->reset(addr, sizeof(T), flags);
- if (status() == DcacheMissStall) {
- //Just do the functional access
+ // translate to physical address
+ Fault fault = xc->translateDataReadReq(memReq);
+
+ // do functional access
+ if (fault == No_Fault)
fault = xc->read(memReq, data);
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
- }
- return fault;
+ if (traceData) {
+ traceData->setAddr(addr);
+ if (fault == No_Fault)
+ traceData->setData(data);
}
- memReq->reset(addr, sizeof(T), flags);
-
- // translate to physical address
- fault = xc->translateDataReadReq(memReq);
-
// if we have a cache, do cache access too
if (fault == No_Fault && dcacheInterface) {
memReq->cmd = Read;
@@ -444,25 +440,11 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
- cacheCompletionEvent.read = true;
memReq->completionEvent = &cacheCompletionEvent;
- //May later want to pass the staticinst as well, so it can call
- //it independantly
lastDcacheStall = curTick;
unscheduleTickEvent();
_status = DcacheMissStall;
}
- else {
- // do functional access
- if (fault == No_Fault)
- fault = xc->read(memReq, data);
-
- if (traceData) {
- traceData->setAddr(addr);
- if (fault == No_Fault)
- traceData->setData(data);
- }
- }
}
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@@ -543,7 +525,6 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents()) {
- cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
unscheduleTickEvent();
@@ -615,7 +596,7 @@ Tick save_cycle = 0;
void
-SimpleCPU::processCacheCompletion(bool read)
+SimpleCPU::processCacheCompletion()
{
switch (status()) {
case IcacheMissStall:
@@ -625,9 +606,6 @@ SimpleCPU::processCacheCompletion(bool read)
break;
case DcacheMissStall:
dcacheStallCycles += curTick - lastDcacheStall;
- if (read) {
- globalsi->execute(this,traceData);
- }
_status = Running;
scheduleTickEvent(1);
break;
@@ -751,7 +729,6 @@ SimpleCPU::tick()
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && icacheInterface->doEvents()) {
- cacheCompletionEvent.read = false;
memReq->completionEvent = &cacheCompletionEvent;
lastIcacheStall = curTick;
unscheduleTickEvent();
@@ -776,8 +753,6 @@ SimpleCPU::tick()
inst = htoa(inst);
StaticInstPtr<TheISA> si(inst);
- globalsi = si;
-
traceData = Trace::getInstRecord(curTick, xc, this, si,
xc->regs.pc);