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authorNathan Binkert <binkertn@umich.edu>2004-06-28 16:49:35 -0400
committerNathan Binkert <binkertn@umich.edu>2004-06-28 16:49:35 -0400
commit838273a196c66f3c6ee834ae865db14f313ef1bc (patch)
tree60e31aec4ac06c862ec92f2091b06399ec879b37 /cpu/simple_cpu/simple_cpu.cc
parent19d5789db1a58747daca88e5cd6580bb95db008e (diff)
downloadgem5-838273a196c66f3c6ee834ae865db14f313ef1bc.tar.xz
fix up the recordEvent stuff to support ignoring events
arch/alpha/ev5.cc: cpu/simple_cpu/simple_cpu.cc: update for new event interface base/stats/events.cc: implement the ignore event function which matches sim objects from which to ignore events. Make insert event like insert data and make it able to insert many events in a single transaction with the database. base/stats/events.hh: Make it possible to ignore events sim/sim_object.cc: make recordEvent a member function of SimObject to implement the ignore function easily sim/sim_object.hh: implement the ignore event stuff in the sim object. This is a bit of a hack, but an easy place to put it. --HG-- extra : convert_revision : ba3f25a14ad03662c53fb35514860d69be8cd4f0
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.cc')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index bf4cbfbe2..2c7f78cff 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -406,7 +406,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
}
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
- Stats::recordEvent("Uncached Read");
+ recordEvent("Uncached Read");
return fault;
}
@@ -494,7 +494,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
*res = memReq->result;
if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
- Stats::recordEvent("Uncached Write");
+ recordEvent("Uncached Write");
return fault;
}