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| author | Erik Hallnor <ehallnor@umich.edu> | 2003-10-16 17:04:18 -0400 |
|---|---|---|
| committer | Erik Hallnor <ehallnor@umich.edu> | 2003-10-16 17:04:18 -0400 |
| commit | 4134477369028e04dd265a43753868c01912c465 (patch) | |
| tree | 23879b12a0c0079848cd97b294d141ae8cc4acde /cpu/simple_cpu/simple_cpu.cc | |
| parent | ea5dc1d5dfabd31bdd62c8435f84ea21bf0f61c7 (diff) | |
| download | gem5-4134477369028e04dd265a43753868c01912c465.tar.xz | |
Add a commited loads event queue similar to the one for commited instructions.
Two new parameters for the CPU models, max_loads_any_thread and max_loads_all_threads.
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Swap out maxReads for the new commited loads model.
--HG--
extra : convert_revision : 35031329bbc476122b2203104537a9f8b46addfa
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.cc')
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index f4fc1b823..28009b7f0 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -104,6 +104,8 @@ SimpleCPU::SimpleCPU(const string &_name, System *_system, Counter max_insts_any_thread, Counter max_insts_all_threads, + Counter max_loads_any_thread, + Counter max_loads_all_threads, AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem, MemInterface *icache_interface, @@ -111,15 +113,19 @@ SimpleCPU::SimpleCPU(const string &_name, int cpu_id, Tick freq) : BaseCPU(_name, /* number_of_threads */ 1, max_insts_any_thread, max_insts_all_threads, + max_loads_any_thread, max_loads_all_threads, _system, cpu_id, freq), #else SimpleCPU::SimpleCPU(const string &_name, Process *_process, Counter max_insts_any_thread, Counter max_insts_all_threads, + Counter max_loads_any_thread, + Counter max_loads_all_threads, MemInterface *icache_interface, MemInterface *dcache_interface) : BaseCPU(_name, /* number_of_threads */ 1, - max_insts_any_thread, max_insts_all_threads), + max_insts_any_thread, max_insts_all_threads, + max_loads_any_thread, max_loads_all_threads), #endif tickEvent(this), xc(NULL), cacheCompletionEvent(this) { @@ -636,6 +642,11 @@ SimpleCPU::tick() numMemRefs++; } + if (si->isLoad()) { + ++numLoad; + comLoadEventQueue[0]->serviceEvents(numLoad); + } + if (traceData) traceData->finalize(); @@ -679,6 +690,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) Param<Counter> max_insts_any_thread; Param<Counter> max_insts_all_threads; + Param<Counter> max_loads_any_thread; + Param<Counter> max_loads_all_threads; #ifdef FULL_SYSTEM SimObjectParam<AlphaItb *> itb; @@ -704,6 +717,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) INIT_PARAM_DFLT(max_insts_all_threads, "terminate when all threads have reached this insn count", 0), + INIT_PARAM_DFLT(max_loads_any_thread, + "terminate when any thread reaches this load count", + 0), + INIT_PARAM_DFLT(max_loads_all_threads, + "terminate when all threads have reached this load count", + 0), #ifdef FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), @@ -730,6 +749,7 @@ CREATE_SIM_OBJECT(SimpleCPU) return new SimpleCPU(getInstanceName(), system, max_insts_any_thread, max_insts_all_threads, + max_loads_any_thread, max_loads_all_threads, itb, dtb, mem, (icache) ? icache->getInterface() : NULL, (dcache) ? dcache->getInterface() : NULL, @@ -738,6 +758,7 @@ CREATE_SIM_OBJECT(SimpleCPU) return new SimpleCPU(getInstanceName(), workload, max_insts_any_thread, max_insts_all_threads, + max_loads_any_thread, max_loads_all_threads, icache->getInterface(), dcache->getInterface()); #endif // FULL_SYSTEM |