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authorErik Hallnor <ehallnor@umich.edu>2003-10-16 17:04:25 -0400
committerErik Hallnor <ehallnor@umich.edu>2003-10-16 17:04:25 -0400
commitaeaf133d271a75d649451290d2b3ea12b2b744ec (patch)
treee8c9103896aa63a77350f6b12849ba45e347f5fc /cpu/simple_cpu/simple_cpu.cc
parenta6788d64dd683c0e7d82f10049d39253c0ea03bb (diff)
parent4134477369028e04dd265a43753868c01912c465 (diff)
downloadgem5-aeaf133d271a75d649451290d2b3ea12b2b744ec.tar.xz
Merge ehallnor@zizzer:/bk/m5
into zizzer.eecs.umich.edu:/y/ehallnor/work/m5 --HG-- extra : convert_revision : 2979dcbf516446b45c7fb94454e4c4f013f480e4
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.cc')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc23
1 files changed, 22 insertions, 1 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index f4fc1b823..28009b7f0 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -104,6 +104,8 @@ SimpleCPU::SimpleCPU(const string &_name,
System *_system,
Counter max_insts_any_thread,
Counter max_insts_all_threads,
+ Counter max_loads_any_thread,
+ Counter max_loads_all_threads,
AlphaItb *itb, AlphaDtb *dtb,
FunctionalMemory *mem,
MemInterface *icache_interface,
@@ -111,15 +113,19 @@ SimpleCPU::SimpleCPU(const string &_name,
int cpu_id, Tick freq)
: BaseCPU(_name, /* number_of_threads */ 1,
max_insts_any_thread, max_insts_all_threads,
+ max_loads_any_thread, max_loads_all_threads,
_system, cpu_id, freq),
#else
SimpleCPU::SimpleCPU(const string &_name, Process *_process,
Counter max_insts_any_thread,
Counter max_insts_all_threads,
+ Counter max_loads_any_thread,
+ Counter max_loads_all_threads,
MemInterface *icache_interface,
MemInterface *dcache_interface)
: BaseCPU(_name, /* number_of_threads */ 1,
- max_insts_any_thread, max_insts_all_threads),
+ max_insts_any_thread, max_insts_all_threads,
+ max_loads_any_thread, max_loads_all_threads),
#endif
tickEvent(this), xc(NULL), cacheCompletionEvent(this)
{
@@ -636,6 +642,11 @@ SimpleCPU::tick()
numMemRefs++;
}
+ if (si->isLoad()) {
+ ++numLoad;
+ comLoadEventQueue[0]->serviceEvents(numLoad);
+ }
+
if (traceData)
traceData->finalize();
@@ -679,6 +690,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
+ Param<Counter> max_loads_any_thread;
+ Param<Counter> max_loads_all_threads;
#ifdef FULL_SYSTEM
SimObjectParam<AlphaItb *> itb;
@@ -704,6 +717,12 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
INIT_PARAM_DFLT(max_insts_all_threads,
"terminate when all threads have reached this insn count",
0),
+ INIT_PARAM_DFLT(max_loads_any_thread,
+ "terminate when any thread reaches this load count",
+ 0),
+ INIT_PARAM_DFLT(max_loads_all_threads,
+ "terminate when all threads have reached this load count",
+ 0),
#ifdef FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
@@ -730,6 +749,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
return new SimpleCPU(getInstanceName(), system,
max_insts_any_thread, max_insts_all_threads,
+ max_loads_any_thread, max_loads_all_threads,
itb, dtb, mem,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL,
@@ -738,6 +758,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
return new SimpleCPU(getInstanceName(), workload,
max_insts_any_thread, max_insts_all_threads,
+ max_loads_any_thread, max_loads_all_threads,
icache->getInterface(), dcache->getInterface());
#endif // FULL_SYSTEM