Changes to use siinic:

Changed SimpleCPU to not due functional access until the cache returns
Updated config file to use a simple cpu for second cpu in dual mode.

cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
    Update cache completion event to perform the functional read upon completion

--HG--
extra : convert_revision : 7a5b318d2040580fae92c165611425f513b14be9

1 files changed, 5 insertions, 1 deletions

diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 341a0da23..64e45d35e 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -184,6 +184,8 @@ class SimpleCPU : public BaseCPU
     // Refcounted pointer to the one memory request.
     MemReqPtr memReq;
 
+    StaticInstPtr<TheISA> globalsi;
+
     class CacheCompletionEvent : public Event
     {
       private:
@@ -192,6 +194,8 @@ class SimpleCPU : public BaseCPU
       public:
         CacheCompletionEvent(SimpleCPU *_cpu);
 
+        bool read;
+
         virtual void process();
         virtual const char *description();
     };
@@ -238,7 +242,7 @@ class SimpleCPU : public BaseCPU
     Stats::Scalar<> dcacheStallCycles;
     Counter lastDcacheStall;
 
-    void processCacheCompletion();
+    void processCacheCompletion(bool read);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);