Do a better job of factoring out CPU model in ISA description.

(Still not perfect though.)

arch/alpha/isa_desc:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.  Force all instruction
    execution context into a single model-dependent class (SimpleCPU itself
    for SimpleCPU, DynInst for FullCPU).
arch/isa_parser.py:
    Do a better job of factoring out CPU model.  (Still not perfect though.)
    Pull execute() methods out of class declarations into separate section
    of file, allowing (1) easier replication for different CPU models and
    (2) a path to putting them all in a separate file.
    Also restructure top level to allow parser to run under interactive
    interpreter session for easier debugging.
cpu/exec_context.hh:
    Add a few new methods to clean up isa_desc.
cpu/simple_cpu/simple_cpu.cc:
cpu/static_inst.hh:
    StaticInst::execute no longer takes a CPU and an ExecContext,
    just a unified FooCPUExecContext.
cpu/simple_cpu/simple_cpu.hh:
    Add methods to redirect calls to ExecContext so SimpleCPU
    can act as sole instruction execution context for itself.
    Typedef SimpleCPU to SimpleCPUExecContext.

--HG--
extra : convert_revision : ecc445503bc585585da5663fe61796580e744da6

1 files changed, 50 insertions, 0 deletions

diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index d634753b9..4977e6992 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -250,6 +250,56 @@ class SimpleCPU : public BaseCPU
     Fault copySrcTranslate(Addr src);
 
     Fault copy(Addr dest);
+
+    uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); }
+
+    float readFloatRegSingle(int reg_idx)
+    { return xc->readFloatRegSingle(reg_idx); }
+
+    double readFloatRegDouble(int reg_idx)
+    { return xc->readFloatRegDouble(reg_idx); }
+
+    uint64_t readFloatRegInt(int reg_idx)
+    { return xc->readFloatRegInt(reg_idx); }
+
+    void setIntReg(int reg_idx, uint64_t val)
+    { return xc->setIntReg(reg_idx, val); }
+
+    void setFloatRegSingle(int reg_idx, float val)
+    { return xc->setFloatRegSingle(reg_idx, val); }
+
+    void setFloatRegDouble(int reg_idx, double val)
+    { return xc->setFloatRegDouble(reg_idx, val); }
+
+    void setFloatRegInt(int reg_idx, uint64_t val)
+    { return xc->setFloatRegInt(reg_idx, val); }
+
+    uint64_t readPC() { return xc->readPC(); }
+    void setNextPC(uint64_t val) { return xc->setNextPC(val); }
+
+    uint64_t readUniq() { return xc->readUniq(); }
+    void setUniq(uint64_t val) { return xc->setUniq(val); }
+
+    uint64_t readFpcr() { return xc->readFpcr(); }
+    void setFpcr(uint64_t val) { return xc->setFpcr(val); }
+
+#ifdef FULL_SYSTEM
+    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
+    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+    Fault hwrei() { return xc->hwrei(); }
+    int readIntrFlag() { return xc->readIntrFlag(); }
+    void setIntrFlag(int val) { xc->setIntrFlag(val); }
+    bool inPalMode() { return xc->inPalMode(); }
+    void ev5_trap(Fault fault) { return xc->ev5_trap(fault); }
+    bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
+#else
+    void syscall() { xc->syscall(); }
+#endif
+
+    bool misspeculating() { return xc->misspeculating(); }
+    ExecContext *xcBase() { return xc; }
 };
 
+typedef SimpleCPU SimpleCPUExecContext;
+
 #endif // __SIMPLE_CPU_HH__