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author | Nathan Binkert <binkertn@umich.edu> | 2004-05-21 13:03:17 -0400 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2004-05-21 13:03:17 -0400 |
commit | b4405682d9f0d7bd01ff461a7e457f8dbbfff1a0 (patch) | |
tree | 95047a24c7b3a0be93afb2a723f13abd07666745 /cpu/simple_cpu/simple_cpu.hh | |
parent | 47604c8c89539df9aa27b7ba5c4523f27a8ec243 (diff) | |
download | gem5-b4405682d9f0d7bd01ff461a7e457f8dbbfff1a0.tar.xz |
Change the namespace Statistics to Stats
--HG--
extra : convert_revision : 3084b292bbe2e8a392af8e99a31763ca0b0a9467
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.hh')
-rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 0c7204fcd..1c6b18d03 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -210,7 +210,7 @@ class SimpleCPU : public BaseCPU // number of simulated instructions Counter numInst; Counter startNumInst; - Statistics::Scalar<> numInsts; + Stats::Scalar<> numInsts; virtual Counter totalInstructions() const { @@ -218,22 +218,22 @@ class SimpleCPU : public BaseCPU } // number of simulated memory references - Statistics::Scalar<> numMemRefs; + Stats::Scalar<> numMemRefs; // number of simulated loads Counter numLoad; Counter startNumLoad; // number of idle cycles - Statistics::Average<> notIdleFraction; - Statistics::Formula idleFraction; + Stats::Average<> notIdleFraction; + Stats::Formula idleFraction; // number of cycles stalled for I-cache misses - Statistics::Scalar<> icacheStallCycles; + Stats::Scalar<> icacheStallCycles; Counter lastIcacheStall; // number of cycles stalled for D-cache misses - Statistics::Scalar<> dcacheStallCycles; + Stats::Scalar<> dcacheStallCycles; Counter lastDcacheStall; void processCacheCompletion(); |