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| author | Ron Dreslinski <rdreslin@umich.edu> | 2004-11-18 06:11:01 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2004-11-18 06:11:01 -0500 |
| commit | bddb7ad7b530a10594a9ad6d07648fb17fea607a (patch) | |
| tree | b783401a62674b387b3f32c0051ead81a3804328 /cpu/simple_cpu/simple_cpu.hh | |
| parent | 25890b94048aba346357f1850767052f4807cc34 (diff) | |
| download | gem5-bddb7ad7b530a10594a9ad6d07648fb17fea607a.tar.xz | |
Put back in SimpleCPU changes and Coherence Timing Bus changes
Small fixes to read() in simpleCPU and small fixes to cache_impl.hh
and to simple_mem_bank to deal with writeInv from DMA
--HG--
extra : convert_revision : db24028c34b7a535aa0db55b43bad1d3d75cd258
Diffstat (limited to 'cpu/simple_cpu/simple_cpu.hh')
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh index 341a0da23..8104d73a4 100644 --- a/cpu/simple_cpu/simple_cpu.hh +++ b/cpu/simple_cpu/simple_cpu.hh @@ -184,6 +184,8 @@ class SimpleCPU : public BaseCPU // Refcounted pointer to the one memory request. MemReqPtr memReq; + StaticInstPtr<TheISA> curStaticInst; + class CacheCompletionEvent : public Event { private: |