merge with m5 head

--HG--
extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311

1 files changed, 11 insertions, 4 deletions

diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 16753fa4f..9edd66ab4 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -133,7 +133,7 @@ class SimpleCPU : public BaseCPU
               Counter max_loads_any_thread, Counter max_loads_all_threads,
               AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
               MemInterface *icache_interface, MemInterface *dcache_interface,
-              Tick freq);
+              bool _def_reg, Tick freq);
 
 #else
 
@@ -142,11 +142,13 @@ class SimpleCPU : public BaseCPU
               Counter max_insts_all_threads,
               Counter max_loads_any_thread,
               Counter max_loads_all_threads,
-              MemInterface *icache_interface, MemInterface *dcache_interface);
+              MemInterface *icache_interface, MemInterface *dcache_interface,
+              bool _def_reg);
 
 #endif
 
     virtual ~SimpleCPU();
+    virtual void init();
 
     // execution context
     ExecContext *xc;
@@ -166,6 +168,8 @@ class SimpleCPU : public BaseCPU
     // L1 data cache
     MemInterface *dcacheInterface;
 
+    bool defer_registration;
+
     // current instruction
     MachInst inst;
 
@@ -233,16 +237,19 @@ class SimpleCPU : public BaseCPU
     Fault write(T data, Addr addr, unsigned flags,
                         uint64_t *res);
 
-    Fault prefetch(Addr addr, unsigned flags)
+    void prefetch(Addr addr, unsigned flags)
     {
         // need to do this...
-        return No_Fault;
     }
 
     void writeHint(Addr addr, int size)
     {
         // need to do this...
     }
+
+    Fault copySrcTranslate(Addr src);
+
+    Fault copy(Addr dest);
 };
 
 #endif // __SIMPLE_CPU_HH__