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authorNathan Binkert <binkertn@umich.edu>2003-11-06 00:41:14 -0500
committerNathan Binkert <binkertn@umich.edu>2003-11-06 00:41:14 -0500
commit655e9ef3de65ce71f63fce23152de862994c38f3 (patch)
tree2dcf58807391d686bf38a600aeffd2fc1c290bd0 /cpu/simple_cpu
parent22658f20987208463bd1f8c2ba88f59374dcca66 (diff)
downloadgem5-655e9ef3de65ce71f63fce23152de862994c38f3.tar.xz
Little fixes to make more of the stats reset correctly.
base/statistics.cc: formatting cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: Make numInsts reset by adding a resetStats function sim/sim_object.cc: Register the reset callback in a slightly cleaner way to avoid potential static member constructor ordering issues --HG-- extra : convert_revision : 408073b4b0397fbf9dfd9c548a313f1c8c3fc031
Diffstat (limited to 'cpu/simple_cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc12
-rw-r--r--cpu/simple_cpu/simple_cpu.hh5
2 files changed, 15 insertions, 2 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 550b6c64f..a63f86098 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -159,7 +159,9 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
memReq->data = new uint8_t[64];
numInst = 0;
+ startNumInst = 0;
numLoad = 0;
+ startNumLoad = 0;
lastIcacheStall = 0;
lastDcacheStall = 0;
@@ -215,6 +217,8 @@ SimpleCPU::execCtxStatusChg(int thread_num) {
void
SimpleCPU::regStats()
{
+ using namespace Statistics;
+
BaseCPU::regStats();
numInsts
@@ -244,11 +248,17 @@ SimpleCPU::regStats()
.prereq(dcacheStallCycles)
;
- numInsts = Statistics::scalar(numInst);
+ numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
simInsts += numInsts;
}
void
+SimpleCPU::resetStats()
+{
+ startNumInst = numInst;
+}
+
+void
SimpleCPU::serialize(ostream &os)
{
SERIALIZE_ENUM(_status);
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index d69d4e8de..b0189349f 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -231,10 +231,12 @@ class SimpleCPU : public BaseCPU
}
// statistics
- void regStats();
+ virtual void regStats();
+ virtual void resetStats();
// number of simulated instructions
Counter numInst;
+ Counter startNumInst;
Statistics::Formula numInsts;
// number of simulated memory references
@@ -242,6 +244,7 @@ class SimpleCPU : public BaseCPU
// number of simulated loads
Counter numLoad;
+ Counter startNumLoad;
// number of idle cycles
Statistics::Average<> idleFraction;