diff options
| author | Erik Hallnor <ehallnor@umich.edu> | 2004-01-25 05:01:00 -0500 |
|---|---|---|
| committer | Erik Hallnor <ehallnor@umich.edu> | 2004-01-25 05:01:00 -0500 |
| commit | 01059eadedebfdc0b567edc844b46c5b02bd3991 (patch) | |
| tree | a2ab98336ce31abe22a7229adc368d2ec3775309 /cpu/simple_cpu | |
| parent | fde0b7bfaf916cd3b1805f2f30ca01f40dd7570b (diff) | |
| download | gem5-01059eadedebfdc0b567edc844b46c5b02bd3991.tar.xz | |
Change the way the hierarchy is separated. Now all virtual functions are in the interfaces. This allows new bus models to be used without major hassle. And I thought it was time to change it all again anyways.
cpu/simple_cpu/simple_cpu.cc:
Switch doEvents to doEvents()
--HG--
extra : convert_revision : 14b9517017e76c7b941247004393bf260f397d9a
Diffstat (limited to 'cpu/simple_cpu')
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index adbd17a35..0d5fc4077 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -349,7 +349,7 @@ SimpleCPU::read(Addr addr, T& data, unsigned flags) // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && dcacheInterface->doEvents) { + if (result != MA_HIT && dcacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastDcacheStall = curTick; unscheduleTickEvent(); @@ -432,7 +432,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && dcacheInterface->doEvents) { + if (result != MA_HIT && dcacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastDcacheStall = curTick; unscheduleTickEvent(); @@ -635,7 +635,7 @@ SimpleCPU::tick() // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && icacheInterface->doEvents) { + if (result != MA_HIT && icacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastIcacheStall = curTick; unscheduleTickEvent(); |