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authorSteve Reinhardt <stever@eecs.umich.edu>2005-06-01 21:44:00 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2005-06-01 21:44:00 -0400
commit8031cd93b53cd3fe17a5a5f21e8e8bd833398e97 (patch)
tree2a50907134c83a47058e563522aff265d2487756 /cpu/simple_cpu
parent3304da9270d4b40f445a5ca94c33d68cc52ccddf (diff)
downloadgem5-8031cd93b53cd3fe17a5a5f21e8e8bd833398e97.tar.xz
Standardize clock parameter names to 'clock'.
Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
Diffstat (limited to 'cpu/simple_cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 06fee208d..f20b537f2 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -831,7 +831,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
- Param<int> cycle_time;
+ Param<int> clock;
SimObjectParam<BaseMem *> icache;
SimObjectParam<BaseMem *> dcache;
@@ -863,7 +863,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
- INIT_PARAM(cycle_time, "cpu cycle time"),
+ INIT_PARAM(clock, "clock speed"),
INIT_PARAM(icache, "L1 instruction cache object"),
INIT_PARAM(dcache, "L1 data cache object"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
@@ -889,7 +889,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
params->deferRegistration = defer_registration;
- params->cycleTime = cycle_time;
+ params->clock = clock;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->icache_interface = (icache) ? icache->getInterface() : NULL;