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authorRon Dreslinski <rdreslin@umich.edu>2006-02-23 17:02:34 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-02-23 17:02:34 -0500
commitb6247c9ea7ddc459a076dddf5e5f330da0211c1e (patch)
tree1172ed1b9d52639378ca15be2e24f442c687f1e9 /cpu/static_inst.cc
parent8fc06589cbf28b2a5bf13384d1c683dc50f68a8a (diff)
downloadgem5-b6247c9ea7ddc459a076dddf5e5f330da0211c1e.tar.xz
Add support for multiple ports on the memory. Hook up simple cpu to memory.
Ready to start testing if I could fix the linking errors I can't ever seem to fix. cpu/simple/cpu.cc: cpu/simple/cpu.hh: Add connecting of ports until builder can handle it. mem/physical.cc: Add function to allocate a port in the object Remove some full_sys stuff untill needed mem/physical.hh: Add function to allocate a port in the object python/m5/objects/BaseCPU.py: Update the params sim/process.cc: Make sure to use the right name (hopefully CPU constructor already called) --HG-- extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
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