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authorTaeho Kgil <tkgil@umich.edu>2004-11-03 17:56:26 -0500
committerTaeho Kgil <tkgil@umich.edu>2004-11-03 17:56:26 -0500
commit129b885abd30e72c0b3e19787da385af4af6e53e (patch)
treec0f5ad10584f9b82401edf5abccb19b0f9e99ae2 /cpu/static_inst.hh
parent78ae8764a9d876d377f3e35de7e412f154402580 (diff)
downloadgem5-129b885abd30e72c0b3e19787da385af4af6e53e.tar.xz
Add Inorder CPU model
SConscript: arch/isa_parser.py: cpu/static_inst.hh: Add inorderCPU --HG-- extra : convert_revision : 141372808fac5f6d125f9051ee0be982d21683aa
Diffstat (limited to 'cpu/static_inst.hh')
-rw-r--r--cpu/static_inst.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 0315ab7a9..46b2e4b19 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -44,6 +44,7 @@ class ExecContext;
class DynInst;
class FastCPU;
class SimpleCPU;
+class InorderCPU;
class SymbolTable;
namespace Trace {
@@ -312,6 +313,12 @@ class StaticInst : public StaticInstBase
*/
virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
+ /**
+ * Execute this instruction under InorderCPU model.
+ */
+ virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
+
+
/**
* Execute this instruction under FastCPU model.
*/