Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

1 files changed, 64 insertions, 52 deletions

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 09eb7efbf..2ed2fe61c 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -36,7 +36,7 @@
 #include "base/refcnt.hh"
 #include "cpu/op_class.hh"
 #include "sim/host.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
@@ -109,10 +109,14 @@ class StaticInstBase : public RefCounted
         IsCall,			///< Subroutine call.
         IsReturn,		///< Subroutine return.
 
+        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
+
         IsThreadSync,	///< Thread synchronization operation.
 
         IsSerializing,	///< Serializes pipeline: won't execute until all
                         /// older instructions have committed.
+        IsSerializeBefore,
+        IsSerializeAfter,
         IsMemBarrier,	///< Is a memory barrier
         IsWriteBarrier,	///< Is a write barrier
 
@@ -196,7 +200,11 @@ class StaticInstBase : public RefCounted
     bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
 
     bool isThreadSync()   const { return flags[IsThreadSync]; }
-    bool isSerializing()  const { return flags[IsSerializing]; }
+    bool isSerializing()  const { return flags[IsSerializing] ||
+                                      flags[IsSerializeBefore] ||
+                                      flags[IsSerializeAfter]; }
+    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
+    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
@@ -208,7 +216,6 @@ class StaticInstBase : public RefCounted
 
 
 // forward declaration
-template <class ISA>
 class StaticInstPtr;
 
 /**
@@ -218,21 +225,20 @@ class StaticInstPtr;
  * that are generic across all ISAs but that differ in details
  * according to the specific ISA being used.
  */
-template <class ISA>
 class StaticInst : public StaticInstBase
 {
   public:
 
     /// Binary machine instruction type.
-    typedef typename ISA::MachInst MachInst;
-    /// Memory address type.
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::MachInst MachInst;
+    /// Binary extended machine instruction type.
+    typedef TheISA::ExtMachInst ExtMachInst;
     /// Logical register index type.
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
 
@@ -247,7 +253,7 @@ class StaticInst : public StaticInstBase
     /// Pointer to a statically allocated "null" instruction object.
     /// Used to give eaCompInst() and memAccInst() something to return
     /// when called on non-memory instructions.
-    static StaticInstPtr<ISA> nullStaticInstPtr;
+    static StaticInstPtr nullStaticInstPtr;
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -256,7 +262,7 @@ class StaticInst : public StaticInstBase
      * just the EA computation.
      */
     virtual const
-    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -265,10 +271,10 @@ class StaticInst : public StaticInstBase
      * just the memory access (not the EA computation).
      */
     virtual const
-    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
-    const MachInst machInst;
+    const ExtMachInst machInst;
 
   protected:
 
@@ -298,7 +304,7 @@ class StaticInst : public StaticInstBase
     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 
     /// Constructor.
-    StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
+    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
         : StaticInstBase(__opClass),
           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
     {
@@ -312,7 +318,11 @@ class StaticInst : public StaticInstBase
             delete cachedDisassembly;
     }
 
-#include "static_inst_impl.hh"
+/**
+ * The execute() signatures are auto-generated by scons based on the
+ * set of CPU models we are compiling in today.
+ */
+#include "cpu/static_inst_exec_sigs.hh"
 
     /**
      * Return the target address for a PC-relative branch.
@@ -364,7 +374,7 @@ class StaticInst : public StaticInstBase
     /// Decoded instruction cache type.
     /// For now we're using a generic hash_map; this seems to work
     /// pretty well.
-    typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
+    typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
 
     /// A cache of decoded instruction objects.
     static DecodeCache decodeCache;
@@ -378,63 +388,40 @@ class StaticInst : public StaticInstBase
     /// Decode a machine instruction.
     /// @param mach_inst The binary instruction to decode.
     /// @retval A pointer to the corresponding StaticInst object.
-    static
-    StaticInstPtr<ISA> decode(MachInst mach_inst)
-    {
-#ifdef DECODE_CACHE_HASH_STATS
-        // Simple stats on decode hash_map.  Turns out the default
-        // hash function is as good as anything I could come up with.
-        const int dump_every_n = 10000000;
-        static int decodes_til_dump = dump_every_n;
-
-        if (--decodes_til_dump == 0) {
-            dumpDecodeCacheStats();
-            decodes_til_dump = dump_every_n;
-        }
-#endif
-
-        typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
-        if (iter != decodeCache.end()) {
-            return iter->second;
-        }
-
-        StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
-        decodeCache[mach_inst] = si;
-        return si;
-    }
+    //This is defined as inline below.
+    static StaticInstPtr decode(ExtMachInst mach_inst);
 };
 
 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 
 /// Reference-counted pointer to a StaticInst object.
-/// This type should be used instead of "StaticInst<ISA> *" so that
+/// This type should be used instead of "StaticInst *" so that
 /// StaticInst objects can be properly reference-counted.
-template <class ISA>
-class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
+class StaticInstPtr : public RefCountingPtr<StaticInst>
 {
   public:
     /// Constructor.
     StaticInstPtr()
-        : RefCountingPtr<StaticInst<ISA> >()
+        : RefCountingPtr<StaticInst>()
     {
     }
 
-    /// Conversion from "StaticInst<ISA> *".
-    StaticInstPtr(StaticInst<ISA> *p)
-        : RefCountingPtr<StaticInst<ISA> >(p)
+    /// Conversion from "StaticInst *".
+    StaticInstPtr(StaticInst *p)
+        : RefCountingPtr<StaticInst>(p)
     {
     }
 
     /// Copy constructor.
     StaticInstPtr(const StaticInstPtr &r)
-        : RefCountingPtr<StaticInst<ISA> >(r)
+        : RefCountingPtr<StaticInst>(r)
     {
     }
 
     /// Construct directly from machine instruction.
-    /// Calls StaticInst<ISA>::decode().
-    StaticInstPtr(typename ISA::MachInst mach_inst)
-        : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
+    /// Calls StaticInst::decode().
+    StaticInstPtr(TheISA::ExtMachInst mach_inst)
+        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
     {
     }
 
@@ -445,4 +432,29 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
     }
 };
 
+inline StaticInstPtr
+StaticInst::decode(StaticInst::ExtMachInst mach_inst)
+{
+#ifdef DECODE_CACHE_HASH_STATS
+    // Simple stats on decode hash_map.  Turns out the default
+    // hash function is as good as anything I could come up with.
+    const int dump_every_n = 10000000;
+    static int decodes_til_dump = dump_every_n;
+
+    if (--decodes_til_dump == 0) {
+        dumpDecodeCacheStats();
+        decodes_til_dump = dump_every_n;
+    }
+#endif
+
+    DecodeCache::iterator iter = decodeCache.find(mach_inst);
+    if (iter != decodeCache.end()) {
+        return iter->second;
+    }
+
+    StaticInstPtr si = TheISA::decodeInst(mach_inst);
+    decodeCache[mach_inst] = si;
+    return si;
+}
+
 #endif // __CPU_STATIC_INST_HH__