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authorSteve Reinhardt <stever@eecs.umich.edu>2006-02-24 08:52:38 -0500
committerSteve Reinhardt <stever@eecs.umich.edu>2006-02-24 08:52:38 -0500
commit7a37037358ae5800d0f6a40130929669d836fe70 (patch)
tree31b2c9f9033585b7c163319c8abcb80aa7bd26f4 /cpu/static_inst.hh
parentf6cac25dcfbeed77642026deb81979f651104efe (diff)
parent51647e7bec8e8607fc5713b4ace2c24ce8a7455a (diff)
downloadgem5-7a37037358ae5800d0f6a40130929669d836fe70.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/multiarch arch/isa_parser.py: SCCS merged --HG-- extra : convert_revision : 080cca7616b37db3bf18976b63b3dbcb47d8b918
Diffstat (limited to 'cpu/static_inst.hh')
-rw-r--r--cpu/static_inst.hh6
1 files changed, 5 insertions, 1 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index db9e73714..5566f2f6d 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -316,7 +316,11 @@ class StaticInst : public StaticInstBase
delete cachedDisassembly;
}
-#include "static_inst_impl.hh"
+/**
+ * The execute() signatures are auto-generated by scons based on the
+ * set of CPU models we are compiling in today.
+ */
+#include "cpu/static_inst_exec_sigs.hh"
/**
* Return the target address for a PC-relative branch.