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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-13 22:21:19 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-13 22:21:19 -0700 |
| commit | af5cdc1d8c42bd28472d1bd7126dd8af7d799aeb (patch) | |
| tree | 3e12401114dc5e3aa93dd8c4279e50329af2a9cc /cpu/static_inst.hh | |
| parent | 35e5d907c46b945021c34f7d1b57a5c98189d566 (diff) | |
| download | gem5-af5cdc1d8c42bd28472d1bd7126dd8af7d799aeb.tar.xz | |
Rename CPU object to FullCPU
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
cpu/static_inst.hh:
CPU -> FullCPU
--HG--
extra : convert_revision : 2bed1ed9372ca9e33f7e391a1aa47bbc02675691
Diffstat (limited to 'cpu/static_inst.hh')
| -rw-r--r-- | cpu/static_inst.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 343a3d9b7..644c7dfc4 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -43,7 +43,7 @@ class ExecContext; class SpecExecContext; class SimpleCPU; -class CPU; +class FullCPU; class DynInst; class SymbolTable; @@ -295,9 +295,9 @@ class StaticInst : public StaticInstBase Trace::InstRecord *traceData) = 0; /** - * Execute this instruction under detailed CPU model. + * Execute this instruction under detailed FullCPU model. */ - virtual Fault execute(CPU *cpu, SpecExecContext *xc, DynInst *dynInst, + virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst, Trace::InstRecord *traceData) = 0; /** |