Make all StaticInst methods const. StaticInst objects represent a

particular binary machine instruction and should be immutable after
they are constructed.

cpu/simple_cpu/simple_cpu.hh:
    Make StaticInst parameters const.

--HG--
extra : convert_revision : e535fa10c842ce173336323f39d9108c1847f8ba

1 files changed, 14 insertions, 10 deletions

diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index c442ada35..75bdcc286 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -285,13 +285,13 @@ class StaticInst : public StaticInstBase
      * String representation of disassembly (lazily evaluated via
      * disassemble()).
      */
-    std::string *cachedDisassembly;
+    mutable std::string *cachedDisassembly;
 
     /**
      * Internal function to generate disassembly string.
      */
-    virtual std::string generateDisassembly(Addr pc,
-                                            const SymbolTable *symtab) = 0;
+    virtual std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 
     /// Constructor.
     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
@@ -311,23 +311,27 @@ class StaticInst : public StaticInstBase
     /**
      * Execute this instruction under SimpleCPU model.
      */
-    virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(SimpleCPU *xc,
+                          Trace::InstRecord *traceData) const = 0;
 
-         /**
+    /**
      * Execute this instruction under InorderCPU model.
      */
-    virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(InorderCPU *xc,
+                          Trace::InstRecord *traceData) const = 0;
 
 
     /**
      * Execute this instruction under FastCPU model.
      */
-    virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(FastCPU *xc,
+                          Trace::InstRecord *traceData) const = 0;
 
     /**
      * Execute this instruction under detailed FullCPU model.
      */
-    virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
+    virtual Fault execute(DynInst *xc,
+                          Trace::InstRecord *traceData) const = 0;
 
     /**
      * Return the target address for a PC-relative branch.
@@ -357,7 +361,7 @@ class StaticInst : public StaticInstBase
      * Return true if the instruction is a control transfer, and if so,
      * return the target address as well.
      */
-    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
+    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
 
     /**
      * Return string representation of disassembled instruction.
@@ -367,7 +371,7 @@ class StaticInst : public StaticInstBase
      * should not be cached, this function should be overridden directly.
      */
     virtual const std::string &disassemble(Addr pc,
-                                           const SymbolTable *symtab = 0)
+                                           const SymbolTable *symtab = 0) const
     {
         if (!cachedDisassembly)
             cachedDisassembly =