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authorKevin Lim <ktlim@umich.edu>2005-01-11 19:00:16 -0500
committerKevin Lim <ktlim@umich.edu>2005-01-11 19:00:16 -0500
commit42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4 (patch)
treeba3d10f448bec63df45dff3bb7f2d6fbd6dcf9c7 /cpu/static_inst.hh
parent202758eea20c092bb85d1886898c3816f377d288 (diff)
parent90d4436351620bd3861013333aabd152d5492df7 (diff)
downloadgem5-42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4.tar.xz
Merge changes.
base/traceflags.py: Merge extra new CPU flags cpu/static_inst.hh: Include all the execute functions in static_inst_impl.hh --HG-- extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
Diffstat (limited to 'cpu/static_inst.hh')
-rw-r--r--cpu/static_inst.hh25
1 files changed, 5 insertions, 20 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 46b2e4b19..c47fa32db 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -40,8 +40,12 @@
#include "targetarch/isa_traits.hh"
// forward declarations
+struct AlphaSimpleImpl;
class ExecContext;
class DynInst;
+template <class Impl>
+class AlphaDynInst;
+
class FastCPU;
class SimpleCPU;
class InorderCPU;
@@ -308,26 +312,7 @@ class StaticInst : public StaticInstBase
delete cachedDisassembly;
}
- /**
- * Execute this instruction under SimpleCPU model.
- */
- virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
-
- /**
- * Execute this instruction under InorderCPU model.
- */
- virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0;
-
-
- /**
- * Execute this instruction under FastCPU model.
- */
- virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0;
-
- /**
- * Execute this instruction under detailed FullCPU model.
- */
- virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
+#include "static_inst_impl.hh"
/**
* Return the target address for a PC-relative branch.