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author | Nathan Binkert <binkertn@umich.edu> | 2005-02-19 11:46:41 -0500 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2005-02-19 11:46:41 -0500 |
commit | 9b1e2db811f86d9911bacaad475d1fec70c4aecd (patch) | |
tree | 8be933fb7dd72899a574fd6386b90d5b78710149 /cpu/trace/opt_cpu.hh | |
parent | f4d3f781f1a36d07700a2af98319b67b179f9e5d (diff) | |
download | gem5-9b1e2db811f86d9911bacaad475d1fec70c4aecd.tar.xz |
Clean up CPU stuff and make it use params structs
cpu/base_cpu.cc:
cpu/base_cpu.hh:
Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
Don't have any default parameters.
cpu/memtest/memtest.hh:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
Convert to use a params struct.
remove default parameters
cpu/simple_cpu/simple_cpu.hh:
convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
this isn't really a cpu. don't derive from BaseCPU
objects/MemTest.mpy:
we only need one max_loads parameter
sim/main.cc:
Don't check for the number of CPUs since we may be doing something
else going on. If we don't have anything to simulate, the
simulator will exit anyway.
--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
Diffstat (limited to 'cpu/trace/opt_cpu.hh')
-rw-r--r-- | cpu/trace/opt_cpu.hh | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh index 847147b3c..7f6aa3e18 100644 --- a/cpu/trace/opt_cpu.hh +++ b/cpu/trace/opt_cpu.hh @@ -32,14 +32,14 @@ * trace to access a fully associative cache with optimal replacement. */ -#ifndef __OPT_CPU_HH__ -#define __OPT_CPU_HH__ +#ifndef __CPU_TRACE_OPT_CPU_HH__ +#define __CPU_TRACE_OPT_CPU_HH__ #include <vector> -#include "cpu/base_cpu.hh" #include "mem/mem_req.hh" // for MemReqPtr #include "sim/eventq.hh" // for Event +#include "sim/sim_object.hh" // Forward Declaration class MemTraceReader; @@ -47,8 +47,9 @@ class MemTraceReader; /** * A CPU object to simulate a fully-associative cache with optimal replacement. */ -class OptCPU : public BaseCPU +class OptCPU : public SimObject { + private: typedef int RefIndex; typedef std::vector<RefIndex> L3Table; @@ -219,4 +220,4 @@ class OptCPU : public BaseCPU void tick(); }; -#endif +#endif // __CPU_TRACE_OPT_CPU_HH__ |