Update tracing functionality and add an ITX trace writer.

SConscript:
    Add build support for ITX trace writer
cpu/trace/reader/itx_reader.cc:
    Handle full 36 bit physical addressses.
cpu/trace/reader/itx_reader.hh:
    Need a string header file here
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    Modify trace CPU to take a single trace and drive an instruction and data interfaces.

--HG--
extra : convert_revision : 4c81f2f9d9341df41f0ae45e4bda49800a43977c

1 files changed, 5 insertions, 19 deletions

diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index 6f3ef50a6..1711646a8 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -55,28 +55,17 @@ class TraceCPU : public BaseCPU
     /** Interface for data trace requests, if any. */
     MemInterface *dcacheInterface;
 
-    /** Instruction reference trace. */
-    MemTraceReader *instTrace;
     /** Data reference trace. */
     MemTraceReader *dataTrace;
 
-    /** Number of Icache read ports. */
-    int icachePorts;
-    /** Number of Dcache read/write ports. */
-    int dcachePorts;
-
     /** Number of outstanding requests. */
     int outstandingRequests;
 
-    /** Cycle of the next instruction request, 0 if not available. */
-    Tick nextInstCycle;
-    /** Cycle of the next data request, 0 if not available. */
-    Tick nextDataCycle;
+    /** Cycle of the next request, 0 if not available. */
+    Tick nextCycle;
 
-    /** Next instruction request. */
-    MemReqPtr nextInstReq;
-    /** Next data request. */
-    MemReqPtr nextDataReq;
+    /** Next request. */
+    MemReqPtr nextReq;
 
     /**
      * Event to call the TraceCPU::tick
@@ -113,10 +102,7 @@ class TraceCPU : public BaseCPU
     TraceCPU(const std::string &name,
              MemInterface *icache_interface,
              MemInterface *dcache_interface,
-             MemTraceReader *inst_trace,
-             MemTraceReader *data_trace,
-             int icache_ports,
-             int dcache_ports);
+             MemTraceReader *data_trace);
 
     /**
      * Perform all the accesses for one cycle.