summaryrefslogtreecommitdiff
path: root/cpu/trace
diff options
context:
space:
mode:
authorErik Hallnor <ehallnor@umich.edu>2004-06-08 19:52:49 -0400
committerErik Hallnor <ehallnor@umich.edu>2004-06-08 19:52:49 -0400
commite7c7c92184e7a077ee0a5a80b62e0d7797d73ddb (patch)
treeeae403f9b526d31dc94fdd50d03a0c130dd118e9 /cpu/trace
parent5f4297e865eab5b28c2c17711ecf590934961335 (diff)
downloadgem5-e7c7c92184e7a077ee0a5a80b62e0d7797d73ddb.tar.xz
Tracing now works for upto 4 threads. Easy change to get it to work for more, but I don't have any test handy to test it.
cpu/trace/reader/m5_reader.cc: Add thread num. cpu/trace/trace_cpu.cc: Increase thread count to 4, might want to make this a parameter (but it only really costs us storage). --HG-- extra : convert_revision : 97cd7843668a3ef85aad06e3180dc04d2ca30ac1
Diffstat (limited to 'cpu/trace')
-rw-r--r--cpu/trace/reader/m5_reader.cc2
-rw-r--r--cpu/trace/trace_cpu.cc7
2 files changed, 5 insertions, 4 deletions
diff --git a/cpu/trace/reader/m5_reader.cc b/cpu/trace/reader/m5_reader.cc
index d6ec7be50..a1ada38a2 100644
--- a/cpu/trace/reader/m5_reader.cc
+++ b/cpu/trace/reader/m5_reader.cc
@@ -61,6 +61,8 @@ M5Reader::getNextReq(MemReqPtr &req)
tmp_req = new MemReq();
tmp_req->paddr = ref.paddr;
tmp_req->asid = ref.asid;
+ // Assume asid == thread_num
+ tmp_req->thread_num = ref.asid;
tmp_req->cmd = (MemCmdEnum)ref.cmd;
tmp_req->size = ref.size;
tmp_req->dest = ref.dest;
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index 6fdc32034..6122fc786 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -50,7 +50,7 @@ TraceCPU::TraceCPU(const string &name,
MemTraceReader *data_trace,
int icache_ports,
int dcache_ports)
- : BaseCPU(name, 1), icacheInterface(icache_interface),
+ : BaseCPU(name, 4), icacheInterface(icache_interface),
dcacheInterface(dcache_interface), instTrace(inst_trace),
dataTrace(data_trace), icachePorts(icache_ports),
dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
@@ -78,10 +78,10 @@ TraceCPU::tick()
while (nextDataReq && (dataReqs < dcachePorts) &&
curTick >= nextDataCycle) {
+ assert(nextDataReq->thread_num < 4 && "Not enough threads");
if (dcacheInterface->isBlocked())
break;
- ++outstandingRequests;
++dataReqs;
nextDataReq->time = curTick;
nextDataReq->completionEvent =
@@ -92,6 +92,7 @@ TraceCPU::tick()
while (nextInstReq && (instReqs < icachePorts) &&
curTick >= nextInstCycle) {
+ assert(nextInstReq->thread_num < 4 && "Not enough threads");
if (icacheInterface->isBlocked())
break;
@@ -99,7 +100,6 @@ TraceCPU::tick()
if (nextInstReq->cmd == Squash) {
icacheInterface->squash(nextInstReq->asid);
} else {
- ++outstandingRequests;
++instReqs;
nextInstReq->completionEvent =
new TraceCompleteEvent(nextInstReq, this);
@@ -124,7 +124,6 @@ TraceCPU::tick()
void
TraceCPU::completeRequest(MemReqPtr& req)
{
- --outstandingRequests;
}
void