Clean up CPU stuff and make it use params structs

cpu/base_cpu.cc:
cpu/base_cpu.hh:
    Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
    Don't have any default parameters.
cpu/memtest/memtest.hh:
    The memory tester is really not a cpu, so don't derive from
    BaseCPU since it just makes things a pain in the butt.  Keep
    track of max loads in the memtest class now that the base class
    doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
    Convert to use a params struct.
    remove default parameters
cpu/simple_cpu/simple_cpu.hh:
    convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
    this isn't really a cpu.  don't derive from BaseCPU
objects/MemTest.mpy:
    we only need one max_loads parameter
sim/main.cc:
    Don't check for the number of CPUs since we may be doing something
    else going on.  If we don't have anything to simulate, the
    simulator will exit anyway.

--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5

4 files changed, 14 insertions, 12 deletions

diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc
index 77211e382..15b53d46e 100644
--- a/cpu/trace/opt_cpu.cc
+++ b/cpu/trace/opt_cpu.cc
@@ -48,7 +48,7 @@ OptCPU::OptCPU(const string &name,
                int block_size,
                int cache_size,
                int _assoc)
-    : BaseCPU(name, 1, true), tickEvent(this), trace(_trace),
+    : SimObject(name), tickEvent(this), trace(_trace),
       numBlks(cache_size/block_size), assoc(_assoc), numSets(numBlks/assoc),
       setMask(numSets - 1)
 {
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index 847147b3c..7f6aa3e18 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -32,14 +32,14 @@
  * trace to access a fully associative cache with optimal replacement.
  */
 
-#ifndef __OPT_CPU_HH__
-#define __OPT_CPU_HH__
+#ifndef __CPU_TRACE_OPT_CPU_HH__
+#define __CPU_TRACE_OPT_CPU_HH__
 
 #include <vector>
 
-#include "cpu/base_cpu.hh"
 #include "mem/mem_req.hh" // for MemReqPtr
 #include "sim/eventq.hh" // for Event
+#include "sim/sim_object.hh"
 
 // Forward Declaration
 class MemTraceReader;
@@ -47,8 +47,9 @@ class MemTraceReader;
 /**
  * A CPU object to simulate a fully-associative cache with optimal replacement.
  */
-class OptCPU : public BaseCPU
+class OptCPU : public SimObject
 {
+  private:
     typedef int RefIndex;
 
     typedef std::vector<RefIndex> L3Table;
@@ -219,4 +220,4 @@ class OptCPU : public BaseCPU
     void tick();
 };
 
-#endif
+#endif // __CPU_TRACE_OPT_CPU_HH__
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index f1160337a..1902d0be4 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -47,7 +47,7 @@ TraceCPU::TraceCPU(const string &name,
                    MemInterface *icache_interface,
                    MemInterface *dcache_interface,
                    MemTraceReader *data_trace)
-    : BaseCPU(name, 4, true), icacheInterface(icache_interface),
+    : SimObject(name), icacheInterface(icache_interface),
       dcacheInterface(dcache_interface),
       dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
 {
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index 1711646a8..cdac4bb4f 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -32,14 +32,14 @@
  * provided memory hierarchy.
  */
 
-#ifndef __TRACE_CPU_HH__
-#define __TRACE_CPU_HH__
+#ifndef __CPU_TRACE_TRACE_CPU_HH__
+#define __CPU_TRACE_TRACE_CPU_HH__
 
 #include <string>
 
-#include "cpu/base_cpu.hh"
 #include "mem/mem_req.hh" // for MemReqPtr
 #include "sim/eventq.hh" // for Event
+#include "sim/sim_object.hh"
 
 // Forward declaration.
 class MemInterface;
@@ -48,8 +48,9 @@ class MemTraceReader;
 /**
  * A cpu object for running memory traces through a memory hierarchy.
  */
-class TraceCPU : public BaseCPU
+class TraceCPU : public SimObject
 {
+  private:
     /** Interface for instruction trace requests, if any. */
     MemInterface *icacheInterface;
     /** Interface for data trace requests, if any. */
@@ -133,5 +134,5 @@ class TraceCompleteEvent : public Event
     virtual const char *description();
 };
 
-#endif //__TRACE_CPU_HH__
+#endif // __CPU_TRACE_TRACE_CPU_HH__