shuffle files around for new directory structure

--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032

80 files changed, 145 insertions, 218 deletions

diff --git a/cpu/base_cpu.cc b/cpu/base.cc
index fd91749f7..91ddc165e 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base.cc
@@ -34,9 +34,9 @@
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
 #include "base/output.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/param.hh"
 #include "sim/sim_events.hh"
 
diff --git a/cpu/base_cpu.hh b/cpu/base.hh
index f38a6c939..0cb81e93b 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base.hh
@@ -26,13 +26,13 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BASE_CPU_HH__
-#define __BASE_CPU_HH__
+#ifndef __CPU_BASE_HH__
+#define __CPU_BASE_HH__
 
 #include <vector>
 
 #include "base/statistics.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
@@ -216,4 +216,4 @@ class BaseCPU : public SimObject
     Stats::Scalar<> numCycles;
 };
 
-#endif // __BASE_CPU_HH__
+#endif // __CPU_BASE_HH__
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 98a4d5b6d..5ad990c72 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -41,8 +41,8 @@
 #include "mem/mem_req.hh"
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
 
 using namespace std;
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index a54e53255..2a5e07894 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -34,16 +34,15 @@
 
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
-
-#include "cpu/beta_cpu/comm.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/bpred_update.hh"
-#include "cpu/full_cpu/op_class.hh"
-#include "cpu/full_cpu/spec_memory.hh"
-#include "cpu/full_cpu/spec_state.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/static_inst.hh"
-#include "mem/functional_mem/main_memory.hh"
+#include "encumbered/cpu/full/bpred_update.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "encumbered/cpu/full/spec_memory.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/mem/functional/main.hh"
 
 /**
  * @file
diff --git a/cpu/beta_cpu/rob.cc b/cpu/beta_cpu/rob.cc
deleted file mode 100644
index ad45c022f..000000000
--- a/cpu/beta_cpu/rob.cc
+++ /dev/null
@@ -1,7 +0,0 @@
-
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/rob_impl.hh"
-
-// Force instantiation of InstructionQueue.
-template class ROB<AlphaSimpleImpl>;
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 1cb33f13e..87b064dbc 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -28,7 +28,7 @@
 
 #include <string>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 
 #ifdef FULL_SYSTEM
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index d6140d52f..3e55cb5c6 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -26,12 +26,12 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __EXEC_CONTEXT_HH__
-#define __EXEC_CONTEXT_HH__
+#ifndef __CPU_EXEC_CONTEXT_HH__
+#define __CPU_EXEC_CONTEXT_HH__
 
-#include "sim/host.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "targetarch/byte_swap.hh"
 
@@ -467,4 +467,4 @@ ExecContext::misspeculating()
     return false;
 }
 
-#endif // __EXEC_CONTEXT_HH__
+#endif // __CPU_EXEC_CONTEXT_HH__
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index 048a7d283..953e1ff06 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -30,13 +30,13 @@
 #include <iomanip>
 
 #include "sim/param.hh"
-#include "cpu/full_cpu/dyn_inst.hh"
-#include "cpu/full_cpu/spec_state.hh"
-#include "cpu/full_cpu/issue.hh"
+#include "encumbered/cpu/full/dyn_inst.hh"
+#include "encumbered/cpu/full/spec_state.hh"
+#include "encumbered/cpu/full/issue.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/exec_context.hh"
 #include "base/loader/symtab.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/static_inst.hh"
 
 using namespace std;
diff --git a/cpu/full_cpu/op_class.hh b/cpu/full_cpu/op_class.hh
deleted file mode 100644
index 8e85e8d8a..000000000
--- a/cpu/full_cpu/op_class.hh
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __OP_CLASS_HH__
-#define __OP_CLASS_HH__
-
-/**
- * @file
- * Definition of operation classes.
- */
-
-/**
- * Instruction operation classes.  These classes are used for
- * assigning instructions to functional units.
- */
-enum OpClass {
-    No_OpClass = 0,	/* inst does not use a functional unit */
-    IntAluOp,		/* integer ALU */
-    IntMultOp,		/* integer multiplier */
-    IntDivOp,		/* integer divider */
-    FloatAddOp,		/* floating point adder/subtractor */
-    FloatCmpOp,		/* floating point comparator */
-    FloatCvtOp,		/* floating point<->integer converter */
-    FloatMultOp,	/* floating point multiplier */
-    FloatDivOp,		/* floating point divider */
-    FloatSqrtOp,	/* floating point square root */
-    MemReadOp,		/* memory read port */
-    MemWriteOp,		/* memory write port */
-    IprAccessOp,	/* Internal Processor Register read/write port */
-    InstPrefetchOp,	/* instruction prefetch port (on I-cache) */
-    Num_OpClasses	/* total functional unit classes */
-};
-
-/**
- * Array mapping OpClass enum values to strings.  Defined in fu_pool.cc.
- */
-extern const char *opClassStrings[];
-
-#endif // __OP_CLASS_HH__
diff --git a/cpu/intr_control.cc b/cpu/intr_control.cc
index 53de9d288..fac0926bf 100644
--- a/cpu/intr_control.cc
+++ b/cpu/intr_control.cc
@@ -29,7 +29,7 @@
 #include <string>
 #include <vector>
 
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/intr_control.hh"
 #include "sim/builder.hh"
 #include "sim/sim_object.hh"
diff --git a/cpu/intr_control.hh b/cpu/intr_control.hh
index 8cdc6b61b..6a43cd933 100644
--- a/cpu/intr_control.hh
+++ b/cpu/intr_control.hh
@@ -31,7 +31,7 @@
 
 #include <vector>
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 #include "cpu/exec_context.hh"
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 86d03e162..728e29ff1 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -39,7 +39,6 @@
 #include "cpu/exec_context.hh"
 #include "cpu/memtest/memtest.hh"
 #include "mem/cache/base_cache.hh"
-#include "mem/functional_mem/main_memory.hh"
 #include "sim/builder.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index ed25cf374..feb50ad9b 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -32,7 +32,7 @@
 #include <set>
 
 #include "base/statistics.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #include "mem/mem_interface.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_exit.hh"
diff --git a/cpu/beta_cpu/2bit_local_pred.cc b/cpu/o3/2bit_local_pred.cc
index e753cbcf3..d9744eec7 100644
--- a/cpu/beta_cpu/2bit_local_pred.cc
+++ b/cpu/o3/2bit_local_pred.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/2bit_local_pred.hh"
+#include "cpu/o3/2bit_local_pred.hh"
 
 DefaultBP::DefaultBP(unsigned _localPredictorSize,
                      unsigned _localCtrBits,
diff --git a/cpu/beta_cpu/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index 945584e04..856407f56 100644
--- a/cpu/beta_cpu/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
 {
diff --git a/cpu/beta_cpu/alpha_full_cpu.cc b/cpu/o3/alpha_cpu.cc
index 862a8cc3f..7bc90dae6 100644
--- a/cpu/beta_cpu/alpha_full_cpu.cc
+++ b/cpu/o3/alpha_cpu.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 // Force instantiation of AlphaFullCPU for all the implemntations that are
 // needed.  Consider merging this and alpha_dyn_inst.cc, and maybe all
diff --git a/cpu/beta_cpu/alpha_full_cpu.hh b/cpu/o3/alpha_cpu.hh
index 4213979d5..386c60b0c 100644
--- a/cpu/beta_cpu/alpha_full_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -32,7 +32,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 #define __CPU_BETA_CPU_ALPHA_FULL_CPU_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 template <class Impl>
 class AlphaFullCPU : public FullBetaCPU<Impl>
diff --git a/cpu/beta_cpu/alpha_full_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index f56c9f6c3..6f4e4f0be 100644
--- a/cpu/beta_cpu/alpha_full_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -26,18 +26,16 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-
-#include "mem/cache/base_cache.hh"
-
 #include "base/inifile.hh"
 #include "base/loader/symtab.hh"
 #include "base/misc.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "mem/base_mem.hh"
+#include "mem/cache/base_cache.hh"
 #include "mem/mem_interface.hh"
 #include "sim/builder.hh"
 #include "sim/debug.hh"
@@ -49,16 +47,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
-#include "dev/pciareg.h"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
diff --git a/cpu/beta_cpu/alpha_full_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 8132ec859..822d58f1f 100644
--- a/cpu/beta_cpu/alpha_full_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -8,9 +8,9 @@
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-#include "cpu/beta_cpu/alpha_params.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
diff --git a/cpu/beta_cpu/alpha_dyn_inst.cc b/cpu/o3/alpha_dyn_inst.cc
index 39759dd88..72ac77d95 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.cc
+++ b/cpu/o3/alpha_dyn_inst.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_dyn_inst_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
 
 // Force instantiation of AlphaDynInst for all the implementations that
 // are needed.
diff --git a/cpu/beta_cpu/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index e4a790119..0b6b62f35 100644
--- a/cpu/beta_cpu/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -30,8 +30,8 @@
 #define __CPU_BETA_CPU_ALPHA_DYN_INST_HH__
 
 #include "cpu/base_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_full_cpu.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_impl.hh"
 #include "cpu/inst_seq.hh"
 
 /**
diff --git a/cpu/beta_cpu/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 66a2cc316..437b113e4 100644
--- a/cpu/beta_cpu/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template <class Impl>
 AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
diff --git a/cpu/beta_cpu/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 173f3b8f7..eb3c07dd3 100644
--- a/cpu/beta_cpu/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -31,8 +31,8 @@
 
 #include "arch/alpha/isa_traits.hh"
 
-#include "cpu/beta_cpu/alpha_params.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/cpu_policy.hh"
 
 // Forward declarations.
 template <class Impl>
diff --git a/cpu/beta_cpu/alpha_params.hh b/cpu/o3/alpha_params.hh
index c0379a4d9..5c8f61f3b 100644
--- a/cpu/beta_cpu/alpha_params.hh
+++ b/cpu/o3/alpha_params.hh
@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 #define __CPU_BETA_CPU_ALPHA_SIMPLE_PARAMS_HH__
 
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/cpu.hh"
 
 //Forward declarations
 class System;
diff --git a/cpu/beta_cpu/bpred_unit.cc b/cpu/o3/bpred_unit.cc
index edf2df65a..85bd6f0a6 100644
--- a/cpu/beta_cpu/bpred_unit.cc
+++ b/cpu/o3/bpred_unit.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/bpred_unit_impl.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
+#include "cpu/o3/bpred_unit_impl.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
 
 template class TwobitBPredUnit<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 960ed500c..0a77b83dc 100644
--- a/cpu/beta_cpu/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -34,10 +34,10 @@
 #include "base/statistics.hh"
 #include "cpu/inst_seq.hh"
 
-#include "cpu/beta_cpu/2bit_local_pred.hh"
-#include "cpu/beta_cpu/tournament_pred.hh"
-#include "cpu/beta_cpu/btb.hh"
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/2bit_local_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
+#include "cpu/o3/btb.hh"
+#include "cpu/o3/ras.hh"
 
 #include <list>
 
diff --git a/cpu/beta_cpu/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index d88c0b391..9cb2e0490 100644
--- a/cpu/beta_cpu/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/bpred_unit.hh"
+#include "cpu/o3/bpred_unit.hh"
 
 template<class Impl>
 TwobitBPredUnit<Impl>::TwobitBPredUnit(Params &params)
diff --git a/cpu/beta_cpu/btb.cc b/cpu/o3/btb.cc
index 92864dbaa..c2bca34ae 100644
--- a/cpu/beta_cpu/btb.cc
+++ b/cpu/o3/btb.cc
@@ -28,7 +28,7 @@
 
 #include "base/intmath.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/btb.hh"
+#include "cpu/o3/btb.hh"
 
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,
diff --git a/cpu/beta_cpu/btb.hh b/cpu/o3/btb.hh
index 66ae931e4..66ae931e4 100644
--- a/cpu/beta_cpu/btb.hh
+++ b/cpu/o3/btb.hh
diff --git a/cpu/beta_cpu/comm.hh b/cpu/o3/comm.hh
index 475ab8df8..475ab8df8 100644
--- a/cpu/beta_cpu/comm.hh
+++ b/cpu/o3/comm.hh
diff --git a/cpu/beta_cpu/commit.cc b/cpu/o3/commit.cc
index 3912be07a..cf33d7f8b 100644
--- a/cpu/beta_cpu/commit.cc
+++ b/cpu/o3/commit.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/commit_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/commit_impl.hh"
 
 template class SimpleCommit<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/commit.hh b/cpu/o3/commit.hh
index 60afe1fd4..60afe1fd4 100644
--- a/cpu/beta_cpu/commit.hh
+++ b/cpu/o3/commit.hh
diff --git a/cpu/beta_cpu/commit_impl.hh b/cpu/o3/commit_impl.hh
index 22ec22c70..ac3d83174 100644
--- a/cpu/beta_cpu/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -27,7 +27,7 @@
  */
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/commit.hh"
+#include "cpu/o3/commit.hh"
 #include "cpu/exetrace.hh"
 
 template <class Impl>
diff --git a/cpu/beta_cpu/full_cpu.cc b/cpu/o3/cpu.cc
index 8eedc3769..a91c36679 100644
--- a/cpu/beta_cpu/full_cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -33,9 +33,9 @@
 #endif
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/full_cpu.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/cpu.hh"
 #include "cpu/exec_context.hh"
 
 using namespace std;
diff --git a/cpu/beta_cpu/full_cpu.hh b/cpu/o3/cpu.hh
index 4ca8ae9ff..df86308a8 100644
--- a/cpu/beta_cpu/full_cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -42,9 +42,9 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/beta_cpu/comm.hh"
-#include "cpu/beta_cpu/cpu_policy.hh"
+#include "cpu/base.hh"
+#include "cpu/o3/comm.hh"
+#include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
diff --git a/cpu/beta_cpu/cpu_policy.hh b/cpu/o3/cpu_policy.hh
index 88e6dca5f..2b53b436d 100644
--- a/cpu/beta_cpu/cpu_policy.hh
+++ b/cpu/o3/cpu_policy.hh
@@ -29,23 +29,23 @@
 #ifndef __CPU_BETA_CPU_CPU_POLICY_HH__
 #define __CPU_BETA_CPU_CPU_POLICY_HH__
 
-#include "cpu/beta_cpu/bpred_unit.hh"
-#include "cpu/beta_cpu/free_list.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
-#include "cpu/beta_cpu/ldstq.hh"
-#include "cpu/beta_cpu/mem_dep_unit.hh"
-#include "cpu/beta_cpu/regfile.hh"
-#include "cpu/beta_cpu/rename_map.hh"
-#include "cpu/beta_cpu/rob.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/bpred_unit.hh"
+#include "cpu/o3/free_list.hh"
+#include "cpu/o3/inst_queue.hh"
+#include "cpu/o3/ldstq.hh"
+#include "cpu/o3/mem_dep_unit.hh"
+#include "cpu/o3/regfile.hh"
+#include "cpu/o3/rename_map.hh"
+#include "cpu/o3/rob.hh"
+#include "cpu/o3/store_set.hh"
 
-#include "cpu/beta_cpu/commit.hh"
-#include "cpu/beta_cpu/decode.hh"
-#include "cpu/beta_cpu/fetch.hh"
-#include "cpu/beta_cpu/iew.hh"
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/commit.hh"
+#include "cpu/o3/decode.hh"
+#include "cpu/o3/fetch.hh"
+#include "cpu/o3/iew.hh"
+#include "cpu/o3/rename.hh"
 
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 struct SimpleCPUPolicy
diff --git a/cpu/beta_cpu/decode.cc b/cpu/o3/decode.cc
index 7e57cd833..290648318 100644
--- a/cpu/beta_cpu/decode.cc
+++ b/cpu/o3/decode.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/decode_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/decode_impl.hh"
 
 template class SimpleDecode<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/decode.hh b/cpu/o3/decode.hh
index 7b89bf288..7b89bf288 100644
--- a/cpu/beta_cpu/decode.hh
+++ b/cpu/o3/decode.hh
diff --git a/cpu/beta_cpu/decode_impl.hh b/cpu/o3/decode_impl.hh
index af848341d..463f0ddac 100644
--- a/cpu/beta_cpu/decode_impl.hh
+++ b/cpu/o3/decode_impl.hh
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/decode.hh"
+#include "cpu/o3/decode.hh"
 
 template<class Impl>
 SimpleDecode<Impl>::SimpleDecode(Params &params)
diff --git a/cpu/beta_cpu/fetch.cc b/cpu/o3/fetch.cc
index 595ab9f8e..8ad5e6565 100644
--- a/cpu/beta_cpu/fetch.cc
+++ b/cpu/o3/fetch.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/fetch_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/fetch_impl.hh"
 
 template class SimpleFetch<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/fetch.hh b/cpu/o3/fetch.hh
index ad0453ed5..ad0453ed5 100644
--- a/cpu/beta_cpu/fetch.hh
+++ b/cpu/o3/fetch.hh
diff --git a/cpu/beta_cpu/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index b49064565..83d7a02e5 100644
--- a/cpu/beta_cpu/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -35,7 +35,7 @@
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
 #include "mem/mem_req.hh"
-#include "cpu/beta_cpu/fetch.hh"
+#include "cpu/o3/fetch.hh"
 
 #include "sim/root.hh"
 
diff --git a/cpu/beta_cpu/free_list.cc b/cpu/o3/free_list.cc
index a670e4af2..6f0b4be1e 100644
--- a/cpu/beta_cpu/free_list.cc
+++ b/cpu/o3/free_list.cc
@@ -28,7 +28,7 @@
 
 #include "base/trace.hh"
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 SimpleFreeList::SimpleFreeList(unsigned _numLogicalIntRegs,
                                unsigned _numPhysicalIntRegs,
diff --git a/cpu/beta_cpu/free_list.hh b/cpu/o3/free_list.hh
index e148acaf2..09d7557a3 100644
--- a/cpu/beta_cpu/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -35,7 +35,7 @@
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 /**
  * FreeList class that simply holds the list of free integer and floating
diff --git a/cpu/beta_cpu/iew.cc b/cpu/o3/iew.cc
index 42436ff20..45b5610e7 100644
--- a/cpu/beta_cpu/iew.cc
+++ b/cpu/o3/iew.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/iew_impl.hh"
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/iew_impl.hh"
+#include "cpu/o3/inst_queue.hh"
 
 template class SimpleIEW<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/iew.hh b/cpu/o3/iew.hh
index 3e5fbe78c..10979801c 100644
--- a/cpu/beta_cpu/iew.hh
+++ b/cpu/o3/iew.hh
@@ -37,7 +37,7 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 template<class Impl>
 class SimpleIEW
diff --git a/cpu/beta_cpu/iew_impl.hh b/cpu/o3/iew_impl.hh
index 39c854833..5f0d7b647 100644
--- a/cpu/beta_cpu/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -34,7 +34,7 @@
 #include <queue>
 
 #include "base/timebuf.hh"
-#include "cpu/beta_cpu/iew.hh"
+#include "cpu/o3/iew.hh"
 
 template<class Impl>
 SimpleIEW<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst,
diff --git a/cpu/beta_cpu/inst_queue.cc b/cpu/o3/inst_queue.cc
index 2362fe252..2ff2282b4 100644
--- a/cpu/beta_cpu/inst_queue.cc
+++ b/cpu/o3/inst_queue.cc
@@ -26,9 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/inst_queue_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
 template class InstructionQueue<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/inst_queue.hh b/cpu/o3/inst_queue.hh
index 02dc1222d..02dc1222d 100644
--- a/cpu/beta_cpu/inst_queue.hh
+++ b/cpu/o3/inst_queue.hh
diff --git a/cpu/beta_cpu/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh
index 51504347a..2221ba456 100644
--- a/cpu/beta_cpu/inst_queue_impl.hh
+++ b/cpu/o3/inst_queue_impl.hh
@@ -38,7 +38,7 @@
 
 #include "sim/root.hh"
 
-#include "cpu/beta_cpu/inst_queue.hh"
+#include "cpu/o3/inst_queue.hh"
 
 // Either compile error or max int due to sign extension.
 // Hack to avoid compile warnings.
diff --git a/cpu/beta_cpu/mem_dep_unit.cc b/cpu/o3/mem_dep_unit.cc
index 9f8831c35..9c1e7f9d8 100644
--- a/cpu/beta_cpu/mem_dep_unit.cc
+++ b/cpu/o3/mem_dep_unit.cc
@@ -26,10 +26,10 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/store_set.hh"
-#include "cpu/beta_cpu/mem_dep_unit_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/store_set.hh"
+#include "cpu/o3/mem_dep_unit_impl.hh"
 
 // Force instantation of memory dependency unit using store sets and
 // AlphaSimpleImpl.
diff --git a/cpu/beta_cpu/mem_dep_unit.hh b/cpu/o3/mem_dep_unit.hh
index f2bb8923a..f2bb8923a 100644
--- a/cpu/beta_cpu/mem_dep_unit.hh
+++ b/cpu/o3/mem_dep_unit.hh
diff --git a/cpu/beta_cpu/mem_dep_unit_impl.hh b/cpu/o3/mem_dep_unit_impl.hh
index e8cd88ba7..296db4c4e 100644
--- a/cpu/beta_cpu/mem_dep_unit_impl.hh
+++ b/cpu/o3/mem_dep_unit_impl.hh
@@ -28,7 +28,7 @@
 
 #include <map>
 
-#include "cpu/beta_cpu/mem_dep_unit.hh"
+#include "cpu/o3/mem_dep_unit.hh"
 
 template <class MemDepPred, class Impl>
 MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params &params)
diff --git a/cpu/beta_cpu/ras.cc b/cpu/o3/ras.cc
index 6b7bf8a09..0a7d6ca63 100644
--- a/cpu/beta_cpu/ras.cc
+++ b/cpu/o3/ras.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/ras.hh"
+#include "cpu/o3/ras.hh"
 
 ReturnAddrStack::ReturnAddrStack(unsigned _numEntries)
     : numEntries(_numEntries), usedEntries(0),
diff --git a/cpu/beta_cpu/ras.hh b/cpu/o3/ras.hh
index d0891a7fb..d0891a7fb 100644
--- a/cpu/beta_cpu/ras.hh
+++ b/cpu/o3/ras.hh
diff --git a/cpu/beta_cpu/regfile.hh b/cpu/o3/regfile.hh
index a41f68e8c..e07944e67 100644
--- a/cpu/beta_cpu/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -33,7 +33,7 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
-#include "cpu/beta_cpu/comm.hh"
+#include "cpu/o3/comm.hh"
 
 #ifdef FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
diff --git a/cpu/beta_cpu/rename.cc b/cpu/o3/rename.cc
index 7f1ba73b6..6e9ee23da 100644
--- a/cpu/beta_cpu/rename.cc
+++ b/cpu/o3/rename.cc
@@ -26,8 +26,8 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/alpha_dyn_inst.hh"
-#include "cpu/beta_cpu/alpha_impl.hh"
-#include "cpu/beta_cpu/rename_impl.hh"
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/rename_impl.hh"
 
 template class SimpleRename<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/rename.hh b/cpu/o3/rename.hh
index 163177d87..163177d87 100644
--- a/cpu/beta_cpu/rename.hh
+++ b/cpu/o3/rename.hh
diff --git a/cpu/beta_cpu/rename_impl.hh b/cpu/o3/rename_impl.hh
index a57f92c78..5fd62e911 100644
--- a/cpu/beta_cpu/rename_impl.hh
+++ b/cpu/o3/rename_impl.hh
@@ -28,7 +28,7 @@
 
 #include <list>
 
-#include "cpu/beta_cpu/rename.hh"
+#include "cpu/o3/rename.hh"
 
 template <class Impl>
 SimpleRename<Impl>::SimpleRename(Params &params)
diff --git a/cpu/beta_cpu/rename_map.cc b/cpu/o3/rename_map.cc
index a8ca88da9..10963f7de 100644
--- a/cpu/beta_cpu/rename_map.cc
+++ b/cpu/o3/rename_map.cc
@@ -28,7 +28,7 @@
 
 #include <vector>
 
-#include "cpu/beta_cpu/rename_map.hh"
+#include "cpu/o3/rename_map.hh"
 
 using namespace std;
 
diff --git a/cpu/beta_cpu/rename_map.hh b/cpu/o3/rename_map.hh
index 46087bae0..48bb3db19 100644
--- a/cpu/beta_cpu/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -37,7 +37,7 @@
 #include <utility>
 #include <vector>
 
-#include "cpu/beta_cpu/free_list.hh"
+#include "cpu/o3/free_list.hh"
 
 class SimpleRenameMap
 {
diff --git a/cpu/o3/rob.cc b/cpu/o3/rob.cc
new file mode 100644
index 000000000..7b590a6fe
--- /dev/null
+++ b/cpu/o3/rob.cc
@@ -0,0 +1,7 @@
+
+#include "cpu/o3/alpha_dyn_inst.hh"
+#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/rob_impl.hh"
+
+// Force instantiation of InstructionQueue.
+template class ROB<AlphaSimpleImpl>;
diff --git a/cpu/beta_cpu/rob.hh b/cpu/o3/rob.hh
index b283e33ca..b283e33ca 100644
--- a/cpu/beta_cpu/rob.hh
+++ b/cpu/o3/rob.hh
diff --git a/cpu/beta_cpu/rob_impl.hh b/cpu/o3/rob_impl.hh
index dd3ffe7e6..6dea46dfc 100644
--- a/cpu/beta_cpu/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -29,7 +29,7 @@
 #ifndef __CPU_BETA_CPU_ROB_IMPL_HH__
 #define __CPU_BETA_CPU_ROB_IMPL_HH__
 
-#include "cpu/beta_cpu/rob.hh"
+#include "cpu/o3/rob.hh"
 
 template <class Impl>
 ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth)
diff --git a/cpu/beta_cpu/sat_counter.cc b/cpu/o3/sat_counter.cc
index 826234703..22fe77e3c 100644
--- a/cpu/beta_cpu/sat_counter.cc
+++ b/cpu/o3/sat_counter.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/misc.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 SatCounter::SatCounter()
     : maxVal(0), counter(0)
diff --git a/cpu/beta_cpu/sat_counter.hh b/cpu/o3/sat_counter.hh
index 5455ca56a..5455ca56a 100644
--- a/cpu/beta_cpu/sat_counter.hh
+++ b/cpu/o3/sat_counter.hh
diff --git a/cpu/beta_cpu/store_set.cc b/cpu/o3/store_set.cc
index 8b9a20c02..11023f4a8 100644
--- a/cpu/beta_cpu/store_set.cc
+++ b/cpu/o3/store_set.cc
@@ -27,7 +27,7 @@
  */
 
 #include "base/trace.hh"
-#include "cpu/beta_cpu/store_set.hh"
+#include "cpu/o3/store_set.hh"
 
 StoreSet::StoreSet(int _SSIT_size, int _LFST_size)
     : SSIT_size(_SSIT_size), LFST_size(_LFST_size)
diff --git a/cpu/beta_cpu/store_set.hh b/cpu/o3/store_set.hh
index 98a92791a..98a92791a 100644
--- a/cpu/beta_cpu/store_set.hh
+++ b/cpu/o3/store_set.hh
diff --git a/cpu/beta_cpu/tournament_pred.cc b/cpu/o3/tournament_pred.cc
index 1b85aee51..3fb580510 100644
--- a/cpu/beta_cpu/tournament_pred.cc
+++ b/cpu/o3/tournament_pred.cc
@@ -26,7 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "cpu/beta_cpu/tournament_pred.hh"
+#include "cpu/o3/tournament_pred.hh"
 
 TournamentBP::TournamentBP(unsigned _local_predictor_size,
                            unsigned _local_ctr_bits,
diff --git a/cpu/beta_cpu/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index d9a14e5c8..feaede369 100644
--- a/cpu/beta_cpu/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -31,7 +31,7 @@
 
 // For Addr type.
 #include "arch/alpha/isa_traits.hh"
-#include "cpu/beta_cpu/sat_counter.hh"
+#include "cpu/o3/sat_counter.hh"
 
 class TournamentBP
 {
diff --git a/cpu/ooo_cpu/ooo_cpu.cc b/cpu/ozone/cpu.cc
index 255070de4..255070de4 100644
--- a/cpu/ooo_cpu/ooo_cpu.cc
+++ b/cpu/ozone/cpu.cc
diff --git a/cpu/ooo_cpu/ooo_cpu.hh b/cpu/ozone/cpu.hh
index ddbc3b061..058279af1 100644
--- a/cpu/ooo_cpu/ooo_cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -30,9 +30,9 @@
 #define __CPU_OOO_CPU_OOO_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
-#include "cpu/full_cpu/fu_pool.hh"
+#include "encumbered/cpu/full/fu_pool.hh"
 #include "cpu/ooo_cpu/ea_list.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/static_inst.hh"
diff --git a/cpu/ooo_cpu/ooo_impl.hh b/cpu/ozone/cpu_impl.hh
index 9e6df9214..9e6df9214 100644
--- a/cpu/ooo_cpu/ooo_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
diff --git a/cpu/ooo_cpu/ea_list.cc b/cpu/ozone/ea_list.cc
index 4142e7f5e..4142e7f5e 100644
--- a/cpu/ooo_cpu/ea_list.cc
+++ b/cpu/ozone/ea_list.cc
diff --git a/cpu/ooo_cpu/ea_list.hh b/cpu/ozone/ea_list.hh
index bc099d7f3..bc099d7f3 100644
--- a/cpu/ooo_cpu/ea_list.hh
+++ b/cpu/ozone/ea_list.hh
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index f30e2a332..7d1e35eba 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -32,7 +32,7 @@
 #include <utility>
 
 #include "base/trace.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
 #include "sim/debug.hh"
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple/cpu.cc
index f20b537f2..306398ac2 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -41,14 +41,14 @@
 #include "base/misc.hh"
 #include "base/pollevent.hh"
 #include "base/range.hh"
-#include "base/trace.hh"
 #include "base/stats/events.hh"
-#include "cpu/base_cpu.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
-#include "cpu/full_cpu/smt.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
-#include "cpu/simple_cpu/simple_cpu.hh"
+#include "cpu/sampler/sampler.hh"
+#include "cpu/simple/cpu.hh"
+#include "cpu/smt.hh"
 #include "cpu/static_inst.hh"
 #include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
@@ -61,16 +61,14 @@
 
 #ifdef FULL_SYSTEM
 #include "base/remote_gdb.hh"
-#include "dev/alpha_access.h"
-#include "dev/pciareg.h"
-#include "mem/functional_mem/memory_control.hh"
-#include "mem/functional_mem/physical_memory.hh"
+#include "mem/functional/memory_control.hh"
+#include "mem/functional/physical.hh"
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
 #include "targetarch/vtophys.hh"
 #else // !FULL_SYSTEM
 #include "eio/eio.hh"
-#include "mem/functional_mem/functional_memory.hh"
+#include "mem/functional/functional.hh"
 #endif // FULL_SYSTEM
 
 using namespace std;
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple/cpu.hh
index 2056ff707..9a0c2952a 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -30,10 +30,10 @@
 #define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
 
 #include "base/statistics.hh"
-#include "cpu/base_cpu.hh"
+#include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
-#include "cpu/sampling_cpu/sampling_cpu.hh"
+#include "cpu/sampler/sampler.hh"
 #include "cpu/static_inst.hh"
 #include "sim/eventq.hh"
 
diff --git a/cpu/full_cpu/smt.hh b/cpu/smt.hh
index 6a4151ffd..6a4151ffd 100644
--- a/cpu/full_cpu/smt.hh
+++ b/cpu/smt.hh
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 4bbe8b636..e80a12960 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -32,11 +32,10 @@
 #include <bitset>
 #include <string>
 
-#include "sim/host.hh"
 #include "base/hashmap.hh"
 #include "base/refcnt.hh"
-
-#include "cpu/full_cpu/op_class.hh"
+#include "encumbered/cpu/full/op_class.hh"
+#include "sim/host.hh"
 #include "targetarch/isa_traits.hh"
 
 // forward declarations