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authorSteve Reinhardt <stever@eecs.umich.edu>2004-05-17 11:49:46 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2004-05-17 11:49:46 -0700
commit1d545281b96a6df358201c7b0e610bfaf9e8f213 (patch)
tree56f869110d789a8efd02a6470b0b74ce718cab68 /cpu
parent32a8827b3ea49fe2c9cd25aa88d7bae2adc6d4e6 (diff)
downloadgem5-1d545281b96a6df358201c7b0e610bfaf9e8f213.tar.xz
Significant changes to ISA description to completely factor
out CPU model. ISA description now generates multiple output source files to (in theory) reduce compilation time. arch/alpha/isa_desc: Update for parser changes. Move most constructors out of class declarations (which are now in decoder.hh) and into decoder.cc. Move all execute() methods into exec output. arch/isa_parser.py: Significant changes to make ISA description completely independent of CPU model, and isolate model-dependent parts of parser into one little class (CpuModel). Also split up code output into multiple files (a header, a main source file, and per-cpu execute() method files). Noticeable changes to language as a result. See updated Doxygen documentation. cpu/simple_cpu/simple_cpu.hh: SimpleCPUExecContext typedef no longer needed. Add forward declaration of Process. cpu/static_inst.hh: SimpleCPUExecContext and FullCPUExecContext typedefs no longer needed. Make eaCompInst() and memAccInst() return const refs. --HG-- extra : convert_revision : 71471f267804fafd0a881bac7445677e76334daf
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.hh9
-rw-r--r--cpu/static_inst.hh14
2 files changed, 12 insertions, 11 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 07d6cb0c9..a04dcd057 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -34,7 +34,7 @@
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "base/statistics.hh"
-
+#include "cpu/exec_context.hh"
// forward declarations
#ifdef FULL_SYSTEM
@@ -46,6 +46,11 @@ class PhysicalMemory;
class RemoteGDB;
class GDBListener;
+
+#else
+
+class Process;
+
#endif // FULL_SYSTEM
class MemInterface;
@@ -305,6 +310,4 @@ class SimpleCPU : public BaseCPU
ExecContext *xcBase() { return xc; }
};
-typedef SimpleCPU SimpleCPUExecContext;
-
#endif // __SIMPLE_CPU_HH__
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 57208f8e6..1065fa3d4 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -42,9 +42,7 @@
// forward declarations
class ExecContext;
class DynInst;
-typedef DynInst FullCPUExecContext;
class SimpleCPU;
-typedef SimpleCPU SimpleCPUExecContext;
class SymbolTable;
namespace Trace {
@@ -249,7 +247,8 @@ class StaticInst : public StaticInstBase
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the EA computation.
*/
- virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
+ virtual const
+ StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
/**
* Memory references only: returns "fake" instruction representing
@@ -257,7 +256,8 @@ class StaticInst : public StaticInstBase
* obtain the dependence info (numSrcRegs and srcRegIdx[]) for
* just the memory access (not the EA computation).
*/
- virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
+ virtual const
+ StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
/// The binary machine instruction.
const MachInst machInst;
@@ -307,14 +307,12 @@ class StaticInst : public StaticInstBase
/**
* Execute this instruction under SimpleCPU model.
*/
- virtual Fault execute(SimpleCPUExecContext *xc,
- Trace::InstRecord *traceData) = 0;
+ virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0;
/**
* Execute this instruction under detailed FullCPU model.
*/
- virtual Fault execute(FullCPUExecContext *xc,
- Trace::InstRecord *traceData) = 0;
+ virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0;
/**
* Return the target address for a PC-relative branch.