Made Addr a global type

--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835

23 files changed, 3 insertions, 44 deletions

diff --git a/cpu/base.hh b/cpu/base.hh
index 311b50f7f..d5764d495 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -48,7 +48,6 @@ class ExecContext;
 class BaseCPU : public SimObject
 {
   protected:
-    typedef TheISA::Addr Addr;
     // CPU's clock period in terms of the number of ticks of curTime.
     Tick clock;
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index dd429fc91..84fd5403e 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -62,8 +62,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     /// Binary machine instruction type.
     typedef TheISA::MachInst MachInst;
-    /// Memory address type.
-    typedef TheISA::Addr Addr;
     /// Logical register index type.
     typedef TheISA::RegIndex RegIndex;
     /// Integer register index type.
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 3c6bad34d..3fa7d078e 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -69,7 +69,6 @@ class ExecContext
 {
   protected:
     typedef TheISA::RegFile RegFile;
-    typedef TheISA::Addr Addr;
     typedef TheISA::MachInst MachInst;
     typedef TheISA::MiscRegFile MiscRegFile;
   public:
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index d37c48ddd..67d042ec8 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -46,7 +46,6 @@ namespace Trace {
 class InstRecord : public Record
 {
   protected:
-    typedef TheISA::Addr Addr;
     typedef TheISA::IntRegFile IntRegFile;
 
     // The following fields are initialized by the constructor and
@@ -172,7 +171,7 @@ inline
 InstRecord *
 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
               const StaticInstPtr staticInst,
-              TheISA::Addr pc, int thread = 0)
+              Addr pc, int thread = 0)
 {
     if (DTRACE(InstExec) &&
         (InstRecord::traceMisspec() || !xc->misspeculating())) {
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 76a89ff2c..7abcf017a 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -42,8 +42,6 @@
 class ExecContext;
 class MemTest : public SimObject
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
 
     MemTest(const std::string &name,
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index 78efe1e43..97433e542 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -35,8 +35,6 @@
 
 class DefaultBP
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index bf3556b8e..2be70f5c2 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -40,7 +40,6 @@ template <class Impl>
 class AlphaFullCPU : public FullO3CPU<Impl>
 {
   protected:
-    typedef AlphaISA::Addr Addr;
     typedef TheISA::IntReg IntReg;
   public:
     typedef typename Impl::Params Params;
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 22be2aae5..b113d9487 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -50,8 +50,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
 
     /** Binary machine instruction type. */
     typedef TheISA::MachInst MachInst;
-    /** Memory address type. */
-    typedef TheISA::Addr	   Addr;
     /** Logical register index type. */
     typedef TheISA::RegIndex RegIndex;
     /** Integer register index type. */
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index c874f9e04..0a77b83dc 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -53,8 +53,6 @@
 template<class Impl>
 class TwobitBPredUnit
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index f443ddbaf..77bdc32ea 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -34,8 +34,6 @@
 
 class DefaultBTB
 {
-  protected:
-    typedef TheISA::Addr Addr;
   private:
     struct BTBEntry
     {
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index bae9a7015..5b9a0f822 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -49,9 +49,6 @@ class SimpleDecode
     typedef typename CPUPol::DecodeStruct DecodeStruct;
     typedef typename CPUPol::TimeStruct TimeStruct;
 
-    // Typedefs from the ISA.
-    typedef TheISA::Addr Addr;
-
   public:
     // The only time decode will become blocked is if dispatch becomes
     // blocked, which means IQ or ROB is probably full.
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index e4d374c1d..82a6cd818 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -61,7 +61,6 @@ class SimpleFetch
 
     /** Typedefs from ISA. */
     typedef TheISA::MachInst MachInst;
-    typedef TheISA::Addr Addr;
 
   public:
     enum Status {
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index fd7f5fe1c..46d98181e 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -34,8 +34,6 @@
 
 class ReturnAddrStack
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
     ReturnAddrStack(unsigned numEntries);
 
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 655a3cad9..021f9b0b6 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -53,7 +53,6 @@ template <class Impl>
 class PhysRegFile
 {
   protected:
-    typedef TheISA::Addr Addr;
     typedef TheISA::IntReg IntReg;
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::MiscRegFile MiscRegFile;
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index 9781480b6..07b442964 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -61,7 +61,6 @@ class SimpleRename
     typedef typename CPUPol::RenameMap RenameMap;
 
     // Typedefs from the ISA.
-    typedef TheISA::Addr Addr;
     typedef TheISA::RegIndex RegIndex;
 
   public:
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index c67d30fcb..5a885d838 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -36,8 +36,6 @@
 
 class StoreSet
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
     typedef unsigned SSID;
 
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 6cfd24cfb..cb93c2f67 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -35,8 +35,6 @@
 
 class TournamentBP
 {
-  protected:
-    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index 7a294866d..83fbc3e2d 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
 #if FULL_SYSTEM
 extern "C"
 void
-sched_break_pc_sys(System *sys, TheISA::Addr addr)
+sched_break_pc_sys(System *sys, Addr addr)
 {
     new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
 }
 
 extern "C"
 void
-sched_break_pc(TheISA::Addr addr)
+sched_break_pc(Addr addr)
 {
      for (vector<System *>::iterator sysi = System::systemList.begin();
           sysi != System::systemList.end(); ++sysi) {
diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh
index 3033a3cfd..7fa3902cc 100644
--- a/cpu/pc_event.hh
+++ b/cpu/pc_event.hh
@@ -39,7 +39,6 @@ class PCEventQueue;
 class PCEvent
 {
   protected:
-    typedef TheISA::Addr Addr;
     static const Addr badpc = MemReq::inval_addr;
 
   protected:
@@ -65,7 +64,6 @@ class PCEvent
 class PCEventQueue
 {
   protected:
-    typedef TheISA::Addr Addr;
     typedef PCEvent * record_t;
     class MapCompare {
       public:
@@ -134,7 +132,6 @@ PCEvent::remove()
 class BreakPCEvent : public PCEvent
 {
   protected:
-    typedef TheISA::Addr Addr;
     bool remove;
 
   public:
diff --git a/cpu/profile.hh b/cpu/profile.hh
index b55f87a6a..18061f9bf 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -37,8 +37,6 @@
 
 class ProfileNode
 {
-  protected:
-    typedef TheISA::Addr Addr;
   private:
     friend class FunctionProfile;
 
@@ -59,8 +57,6 @@ class ProfileNode
 class Callback;
 class FunctionProfile
 {
-  public:
-    typedef TheISA::Addr Addr;
   private:
     Callback *reset;
     const SymbolTable *symtab;
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 1ff14df08..5106dcf06 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -229,8 +229,6 @@ class StaticInst : public StaticInstBase
 
     /// Binary machine instruction type.
     typedef TheISA::MachInst MachInst;
-    /// Memory address type.
-    typedef TheISA::Addr	   Addr;
     /// Logical register index type.
     typedef TheISA::RegIndex RegIndex;
 
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index 704dc09fa..f81691733 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -49,8 +49,6 @@ class MemTraceReader;
  */
 class OptCPU : public SimObject
 {
-  protected:
-    typedef TheISA::Addr Addr;
   private:
     typedef int RefIndex;
 
diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh
index e402b2d52..a16a08085 100644
--- a/cpu/trace/reader/itx_reader.hh
+++ b/cpu/trace/reader/itx_reader.hh
@@ -46,8 +46,6 @@
  */
 class ITXReader : public MemTraceReader
 {
-  protected:
-    typedef TheISA::Addr Addr;
   private:
     /** Trace file. */
     FILE *trace;