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authorAli Saidi <saidi@eecs.umich.edu>2004-06-22 13:48:49 -0400
committerAli Saidi <saidi@eecs.umich.edu>2004-06-22 13:48:49 -0400
commit4deb81989496b360500985377e8f8c1a2f017b27 (patch)
tree20e9a164feb1631c965999ba738999abc4b0a691 /cpu
parent074969f8f16110680de05fca64a6be48aedcdfd8 (diff)
parentc1e58b6bf6b353f9355aafd8ed2cb86e6d00e32a (diff)
downloadgem5-4deb81989496b360500985377e8f8c1a2f017b27.tar.xz
pull from head before pushing linux tree
--HG-- extra : convert_revision : 345f91c5c16c69db22035dc716e82fd77041380f
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.hh2
-rw-r--r--cpu/static_inst.hh3
-rw-r--r--cpu/trace/reader/ibm_reader.cc120
-rw-r--r--cpu/trace/reader/ibm_reader.hh73
-rw-r--r--cpu/trace/reader/itx_reader.cc198
-rw-r--r--cpu/trace/reader/itx_reader.hh82
-rw-r--r--cpu/trace/reader/m5_reader.cc95
-rw-r--r--cpu/trace/reader/m5_reader.hh67
-rw-r--r--cpu/trace/reader/mem_trace_reader.cc37
-rw-r--r--cpu/trace/reader/mem_trace_reader.hh57
-rw-r--r--cpu/trace/trace_cpu.cc191
-rw-r--r--cpu/trace/trace_cpu.hh151
12 files changed, 1073 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 6639dbc1a..3692ab511 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -253,7 +253,7 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
- void writeHint(Addr addr, int size)
+ void writeHint(Addr addr, int size, unsigned flags)
{
// need to do this...
}
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 9a0425c8f..0315ab7a9 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -72,8 +72,7 @@ class StaticInstBase : public RefCounted
/// unconditional branches, memory barriers) or both (e.g., an
/// FP/int conversion).
/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set. Prefetches are marked as IsLoad, even if they
- /// prefetch exclusive copies.
+ /// will be set.
/// - If IsControl is set, then exactly one of IsDirectControl or
/// IsIndirect Control will be set, and exactly one of
/// IsCondControl or IsUncondControl will be set.
diff --git a/cpu/trace/reader/ibm_reader.cc b/cpu/trace/reader/ibm_reader.cc
new file mode 100644
index 000000000..439931dba
--- /dev/null
+++ b/cpu/trace/reader/ibm_reader.cc
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a IBM memory trace format reader.
+ */
+#include <sstream>
+
+#include "cpu/trace/reader/ibm_reader.hh"
+#include "sim/builder.hh"
+#include "base/misc.hh" // for fatal
+
+using namespace std;
+
+IBMReader::IBMReader(const string &name, const string &filename)
+ : MemTraceReader(name)
+{
+ if (strcmp((filename.c_str() + filename.length() -3), ".gz") == 0) {
+ // Compressed file, need to use a pipe to gzip.
+ stringstream buf;
+ buf << "gzip -d -c " << filename << endl;
+ trace = popen(buf.str().c_str(), "r");
+ } else {
+ trace = fopen(filename.c_str(), "rb");
+ }
+ if (!trace) {
+ fatal("Can't open file %s", filename);
+ }
+}
+
+Tick
+IBMReader::getNextReq(MemReqPtr &req)
+{
+ MemReqPtr tmp_req;
+
+ int c = getc(trace);
+ if (c != EOF) {
+ tmp_req = new MemReq();
+ //int cpu_id = (c & 0xf0) >> 4;
+ int type = c & 0x0f;
+ // We have L1 miss traces, so all accesses are 128 bytes
+ tmp_req->size = 128;
+
+ tmp_req->paddr = 0;
+ for (int i = 2; i >= 0; --i) {
+ c = getc(trace);
+ if (c == EOF) {
+ fatal("Unexpected end of file");
+ }
+ tmp_req->paddr |= ((c & 0xff) << (8 * i));
+ }
+ tmp_req->paddr = tmp_req->paddr << 7;
+
+ switch(type) {
+ case IBM_COND_EXCLUSIVE_FETCH:
+ case IBM_READ_ONLY_FETCH:
+ tmp_req->cmd = Read;
+ break;
+ case IBM_EXCLUSIVE_FETCH:
+ case IBM_FETCH_NO_DATA:
+ tmp_req->cmd = Write;
+ break;
+ case IBM_INST_FETCH:
+ tmp_req->cmd = Read;
+ break;
+ default:
+ fatal("Unknown trace entry type.");
+ }
+
+ }
+ req = tmp_req;
+ return 0;
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
+
+ Param<string> filename;
+
+END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
+
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
+
+ INIT_PARAM(filename, "trace file")
+
+END_INIT_SIM_OBJECT_PARAMS(IBMReader)
+
+
+CREATE_SIM_OBJECT(IBMReader)
+{
+ return new IBMReader(getInstanceName(), filename);
+}
+
+REGISTER_SIM_OBJECT("IBMReader", IBMReader)
diff --git a/cpu/trace/reader/ibm_reader.hh b/cpu/trace/reader/ibm_reader.hh
new file mode 100644
index 000000000..0f14da24d
--- /dev/null
+++ b/cpu/trace/reader/ibm_reader.hh
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Definition of a IBM memory trace format reader.
+ */
+
+#ifndef __IBM_READER_HH__
+#define __IBM_READER_HH__
+
+#include <stdio.h>
+#include "cpu/trace/reader/mem_trace_reader.hh"
+#include "mem/mem_req.hh"
+
+/**
+ * A memory trace reader for the IBM memory trace format.
+ */
+class IBMReader : public MemTraceReader
+{
+ /** IBM trace file. */
+ FILE* trace;
+
+ enum IBMType {
+ IBM_INST_FETCH,
+ IBM_READ_ONLY_FETCH,
+ IBM_COND_EXCLUSIVE_FETCH,
+ IBM_EXCLUSIVE_FETCH,
+ IBM_FETCH_NO_DATA
+ };
+
+ public:
+ /**
+ * Construct an IBMReader.
+ */
+ IBMReader(const std::string &name, const std::string &filename);
+
+ /**
+ * Read the next request from the trace. Returns the request in the
+ * provided MemReqPtr and the cycle of the request in the return value.
+ * @param req Return the next request from the trace.
+ * @return IBM traces don't store timing information, return 0
+ */
+ virtual Tick getNextReq(MemReqPtr &req);
+};
+
+#endif //__IBM_READER_HH__
+
diff --git a/cpu/trace/reader/itx_reader.cc b/cpu/trace/reader/itx_reader.cc
new file mode 100644
index 000000000..54bbbc4ea
--- /dev/null
+++ b/cpu/trace/reader/itx_reader.cc
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a Intel ITX memory trace format reader.
+ */
+#include <sstream>
+
+#include "cpu/trace/reader/itx_reader.hh"
+#include "sim/builder.hh"
+#include "base/misc.hh" // for fatal
+
+using namespace std;
+
+ITXReader::ITXReader(const string &name, const string &filename)
+ : MemTraceReader(name)
+{
+ if (strcmp((filename.c_str() + filename.length() -3), ".gz") == 0) {
+ // Compressed file, need to use a pipe to gzip.
+ stringstream buf;
+ buf << "gzip -d -c " << filename << endl;
+ trace = popen(buf.str().c_str(), "r");
+ } else {
+ trace = fopen(filename.c_str(), "rb");
+ }
+ if (!trace) {
+ fatal("Can't open file %s", filename);
+ }
+ traceFormat = 0;
+ int c;
+ for (int i = 0; i < 4; ++i) {
+ c = getc(trace);
+ if (c == EOF) {
+ fatal("Unexpected end of trace file.");
+ }
+ traceFormat |= (c & 0xff) << (8 * i);
+ }
+ if (traceFormat > 2)
+ fatal("Invalid trace format.");
+}
+
+Tick
+ITXReader::getNextReq(MemReqPtr &req)
+{
+ MemReqPtr tmp_req = new MemReq();
+ bool phys_val;
+ do {
+ int c = getc(trace);
+ if (c != EOF) {
+ // Decode first byte
+ // phys_val<1> | type <2:0> | size <3:0>
+ phys_val = c & 0x80;
+ tmp_req->size = (c & 0x0f) + 1;
+ int type = (c & 0x70) >> 4;
+
+ // Could be a compressed instruction entry, expand if necessary
+ if (type == ITXCodeComp) {
+ if (traceFormat != 2) {
+ fatal("Compressed code entry in non CompCode trace.");
+ }
+ if (!codeVirtValid) {
+ fatal("Corrupt CodeComp entry.");
+ }
+
+ tmp_req->vaddr = codeVirtAddr;
+ codeVirtAddr += tmp_req->size;
+ if (phys_val) {
+ if (!codePhysValid) {
+ fatal("Corrupt CodeComp entry.");
+ }
+ tmp_req->paddr = codePhysAddr;
+ if (((tmp_req->paddr & 0xfff) + tmp_req->size) & ~0xfff) {
+ // Crossed page boundary, next physical address is
+ // invalid
+ codePhysValid = false;
+ } else {
+ codePhysAddr += tmp_req->size;
+ }
+ } else {
+ codePhysValid = false;
+ }
+ type = ITXCode;
+ tmp_req->cmd = Read;
+ } else {
+ // Normal entry
+ tmp_req->vaddr = 0;
+ for (int i = 0; i < 4; ++i) {
+ c = getc(trace);
+ if (c == EOF) {
+ fatal("Unexpected end of trace file.");
+ }
+ tmp_req->vaddr |= (c & 0xff) << (8 * i);
+ }
+ if (type == ITXCode) {
+ codeVirtAddr = tmp_req->vaddr + tmp_req->size;
+ codeVirtValid = true;
+ }
+ tmp_req->paddr = 0;
+ if (phys_val) {
+ c = getc(trace);
+ if (c == EOF) {
+ fatal("Unexpected end of trace file.");
+ }
+ // Get the page offset from the virtual address.
+ tmp_req->paddr = tmp_req->vaddr & 0xfff;
+ tmp_req->paddr |= (c & 0xf0) << 8;
+ for (int i = 2; i < 4; ++i) {
+ c = getc(trace);
+ if (c == EOF) {
+ fatal("Unexpected end of trace file.");
+ }
+ tmp_req->paddr |= (c & 0xff) << (8 * i);
+ }
+ if (type == ITXCode) {
+ if (((tmp_req->paddr & 0xfff) + tmp_req->size)
+ & ~0xfff) {
+ // Crossing the page boundary, next physical
+ // address isn't valid
+ codePhysValid = false;
+ } else {
+ codePhysAddr = tmp_req->paddr + tmp_req->size;
+ codePhysValid = true;
+ }
+ }
+ } else if (type == ITXCode) {
+ codePhysValid = false;
+ }
+ switch(type) {
+ case ITXRead:
+ tmp_req->cmd = Read;
+ break;
+ case ITXWrite:
+ tmp_req->cmd = Write;
+ break;
+ case ITXCode:
+ tmp_req->cmd = Read;
+ break;
+ default:
+ fatal("Unknown ITX type");
+ }
+ }
+ } else {
+ // EOF need to return a null request
+ MemReqPtr null_req;
+ req = null_req;
+ return 0;
+ }
+ } while (!phys_val);
+ req = tmp_req;
+ return 0;
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
+
+ Param<string> filename;
+
+END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
+
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
+
+ INIT_PARAM(filename, "trace file")
+
+END_INIT_SIM_OBJECT_PARAMS(ITXReader)
+
+
+CREATE_SIM_OBJECT(ITXReader)
+{
+ return new ITXReader(getInstanceName(), filename);
+}
+
+REGISTER_SIM_OBJECT("ITXReader", ITXReader)
diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh
new file mode 100644
index 000000000..ff74062ea
--- /dev/null
+++ b/cpu/trace/reader/itx_reader.hh
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Definition of a Intel ITX memory trace format reader.
+ */
+
+#ifndef __ITX_READER_HH__
+#define __ITX_READER_HH__
+
+#include <stdio.h>
+
+#include "cpu/trace/reader/mem_trace_reader.hh"
+#include "mem/mem_req.hh"
+
+
+/**
+ * A memory trace reader for the Intel ITX memory trace format.
+ */
+class ITXReader : public MemTraceReader
+{
+ /** Trace file. */
+ FILE *trace;
+
+ bool codeVirtValid;
+ Addr codeVirtAddr;
+ bool codePhysValid;
+ Addr codePhysAddr;
+
+ int traceFormat;
+
+ enum ITXType {
+ ITXRead,
+ ITXWrite,
+ ITXWriteback,
+ ITXCode,
+ ITXCodeComp
+ };
+
+ public:
+ /**
+ * Construct an ITXReader.
+ */
+ ITXReader(const std::string &name, const std::string &filename);
+
+ /**
+ * Read the next request from the trace. Returns the request in the
+ * provided MemReqPtr and the cycle of the request in the return value.
+ * @param req Return the next request from the trace.
+ * @return ITX traces don't store timing information, return 0
+ */
+ virtual Tick getNextReq(MemReqPtr &req);
+};
+
+#endif //__ITX_READER_HH__
+
diff --git a/cpu/trace/reader/m5_reader.cc b/cpu/trace/reader/m5_reader.cc
new file mode 100644
index 000000000..a1ada38a2
--- /dev/null
+++ b/cpu/trace/reader/m5_reader.cc
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a memory trace reader for a M5 memory trace.
+ */
+
+#include "cpu/trace/reader/m5_reader.hh"
+#include "mem/trace/m5_format.hh"
+#include "mem/mem_cmd.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+
+M5Reader::M5Reader(const string &name, const string &filename)
+ : MemTraceReader(name)
+{
+ traceFile.open(filename.c_str(), ios::binary);
+}
+
+Tick
+M5Reader::getNextReq(MemReqPtr &req)
+{
+ M5Format ref;
+
+ MemReqPtr tmp_req;
+ // Need to read EOF char before eof() will return true.
+ traceFile.read((char*) &ref, sizeof(ref));
+ if (!traceFile.eof()) {
+ //traceFile.read((char*) &ref, sizeof(ref));
+ int gcount = traceFile.gcount();
+ assert(gcount != 0 || traceFile.eof());
+ assert(gcount == sizeof(ref));
+ assert(ref.cmd < 12);
+ tmp_req = new MemReq();
+ tmp_req->paddr = ref.paddr;
+ tmp_req->asid = ref.asid;
+ // Assume asid == thread_num
+ tmp_req->thread_num = ref.asid;
+ tmp_req->cmd = (MemCmdEnum)ref.cmd;
+ tmp_req->size = ref.size;
+ tmp_req->dest = ref.dest;
+ } else {
+ ref.cycle = 0;
+ }
+ req = tmp_req;
+ return ref.cycle;
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
+
+ Param<string> filename;
+
+END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
+
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
+
+ INIT_PARAM(filename, "trace file")
+
+END_INIT_SIM_OBJECT_PARAMS(M5Reader)
+
+
+CREATE_SIM_OBJECT(M5Reader)
+{
+ return new M5Reader(getInstanceName(), filename);
+}
+
+REGISTER_SIM_OBJECT("M5Reader", M5Reader)
diff --git a/cpu/trace/reader/m5_reader.hh b/cpu/trace/reader/m5_reader.hh
new file mode 100644
index 000000000..d78787461
--- /dev/null
+++ b/cpu/trace/reader/m5_reader.hh
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Definition of a memory trace reader for a M5 memory trace.
+ */
+
+#ifndef __M5_READER_HH__
+#define __M5_READER_HH__
+
+#include <fstream>
+
+#include "cpu/trace/reader/mem_trace_reader.hh"
+
+/**
+ * A memory trace reader for an M5 memory trace. @sa M5Writer.
+ */
+class M5Reader : public MemTraceReader
+{
+ /** The traceFile. */
+ std::ifstream traceFile;
+
+ std::string fn;
+
+ public:
+ /**
+ * Construct an M5 memory trace reader.
+ */
+ M5Reader(const std::string &name, const std::string &filename);
+
+
+ /**
+ * Read the next request from the trace. Returns the request in the
+ * provided MemReqPtr and the cycle of the request in the return value.
+ * @param req Return the next request from the trace.
+ * @return The cycle the reference was started.
+ */
+ virtual Tick getNextReq(MemReqPtr &req);
+};
+
+#endif // __M5_READER_HH__
diff --git a/cpu/trace/reader/mem_trace_reader.cc b/cpu/trace/reader/mem_trace_reader.cc
new file mode 100644
index 000000000..c6fc53f51
--- /dev/null
+++ b/cpu/trace/reader/mem_trace_reader.cc
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * SimObject Declaration of pure virtual MemTraceReader class.
+ */
+
+#include "cpu/trace/reader/mem_trace_reader.hh"
+#include "sim/param.hh"
+
+DEFINE_SIM_OBJECT_CLASS_NAME("MemTraceReader", MemTraceReader);
diff --git a/cpu/trace/reader/mem_trace_reader.hh b/cpu/trace/reader/mem_trace_reader.hh
new file mode 100644
index 000000000..5da99a498
--- /dev/null
+++ b/cpu/trace/reader/mem_trace_reader.hh
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * Definitions for a pure virtual interface to a memory trace reader.
+ */
+
+#ifndef __MEM_TRACE_READER_HH__
+#define __MEM_TRACE_READER_HH__
+
+#include "sim/sim_object.hh"
+#include "mem/mem_req.hh" // For MemReqPtr
+
+/**
+ * Pure virtual base class for memory trace readers.
+ */
+class MemTraceReader : public SimObject
+{
+ public:
+ /** Construct this MemoryTrace reader. */
+ MemTraceReader(const std::string &name) : SimObject(name) {}
+
+ /**
+ * Read the next request from the trace. Returns the request in the
+ * provided MemReqPtr and the cycle of the request in the return value.
+ * @param req Return the next request from the trace.
+ * @return The cycle of the request, 0 if none in trace.
+ */
+ virtual Tick getNextReq(MemReqPtr &req) = 0;
+};
+
+#endif //__MEM_TRACE_READER_HH__
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
new file mode 100644
index 000000000..6122fc786
--- /dev/null
+++ b/cpu/trace/trace_cpu.cc
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a memory trace CPU object. Uses a memory trace to drive the
+ * provided memory hierarchy.
+ */
+
+#include <algorithm> // For min
+
+#include "cpu/trace/trace_cpu.hh"
+#include "cpu/trace/reader/mem_trace_reader.hh"
+#include "mem/base_mem.hh" // For PARAM constructor
+#include "mem/mem_interface.hh"
+#include "sim/builder.hh"
+#include "sim/sim_events.hh"
+
+using namespace std;
+
+TraceCPU::TraceCPU(const string &name,
+ MemInterface *icache_interface,
+ MemInterface *dcache_interface,
+ MemTraceReader *inst_trace,
+ MemTraceReader *data_trace,
+ int icache_ports,
+ int dcache_ports)
+ : BaseCPU(name, 4), icacheInterface(icache_interface),
+ dcacheInterface(dcache_interface), instTrace(inst_trace),
+ dataTrace(data_trace), icachePorts(icache_ports),
+ dcachePorts(dcache_ports), outstandingRequests(0), tickEvent(this)
+{
+ if (instTrace) {
+ assert(icacheInterface);
+ nextInstCycle = instTrace->getNextReq(nextInstReq);
+ }
+ if (dataTrace) {
+ assert(dcacheInterface);
+ nextDataCycle = dataTrace->getNextReq(nextDataReq);
+ }
+ tickEvent.schedule(0);
+}
+
+void
+TraceCPU::tick()
+{
+ assert(outstandingRequests >= 0);
+ assert(outstandingRequests < 1000);
+ int instReqs = 0;
+ int dataReqs = 0;
+
+ // Do data first to match tracing with FullCPU dumps
+
+ while (nextDataReq && (dataReqs < dcachePorts) &&
+ curTick >= nextDataCycle) {
+ assert(nextDataReq->thread_num < 4 && "Not enough threads");
+ if (dcacheInterface->isBlocked())
+ break;
+
+ ++dataReqs;
+ nextDataReq->time = curTick;
+ nextDataReq->completionEvent =
+ new TraceCompleteEvent(nextDataReq, this);
+ dcacheInterface->access(nextDataReq);
+ nextDataCycle = dataTrace->getNextReq(nextDataReq);
+ }
+
+ while (nextInstReq && (instReqs < icachePorts) &&
+ curTick >= nextInstCycle) {
+ assert(nextInstReq->thread_num < 4 && "Not enough threads");
+ if (icacheInterface->isBlocked())
+ break;
+
+ nextInstReq->time = curTick;
+ if (nextInstReq->cmd == Squash) {
+ icacheInterface->squash(nextInstReq->asid);
+ } else {
+ ++instReqs;
+ nextInstReq->completionEvent =
+ new TraceCompleteEvent(nextInstReq, this);
+ icacheInterface->access(nextInstReq);
+ }
+ nextInstCycle = instTrace->getNextReq(nextInstReq);
+ }
+
+ if (!nextInstReq && !nextDataReq) {
+ // No more requests to send. Finish trailing events and exit.
+ if (mainEventQueue.empty()) {
+ new SimExitEvent("Finshed Memory Trace");
+ } else {
+ tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
+ }
+ } else {
+ tickEvent.schedule(max(curTick + 1,
+ min(nextInstCycle, nextDataCycle)));
+ }
+}
+
+void
+TraceCPU::completeRequest(MemReqPtr& req)
+{
+}
+
+void
+TraceCompleteEvent::process()
+{
+ tester->completeRequest(req);
+}
+
+const char *
+TraceCompleteEvent::description()
+{
+ return "trace access complete";
+}
+
+TraceCPU::TickEvent::TickEvent(TraceCPU *c)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
+{
+}
+
+void
+TraceCPU::TickEvent::process()
+{
+ cpu->tick();
+}
+
+const char *
+TraceCPU::TickEvent::description()
+{
+ return "TraceCPU tick event";
+}
+
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
+
+ SimObjectParam<BaseMem *> icache;
+ SimObjectParam<BaseMem *> dcache;
+ SimObjectParam<MemTraceReader *> inst_trace;
+ SimObjectParam<MemTraceReader *> data_trace;
+ Param<int> inst_ports;
+ Param<int> data_ports;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
+
+ INIT_PARAM_DFLT(icache, "instruction cache", NULL),
+ INIT_PARAM_DFLT(dcache, "data cache", NULL),
+ INIT_PARAM_DFLT(inst_trace, "instruction trace", NULL),
+ INIT_PARAM_DFLT(data_trace, "data trace", NULL),
+ INIT_PARAM_DFLT(inst_ports, "instruction cache read ports", 4),
+ INIT_PARAM_DFLT(data_ports, "data cache read/write ports", 4)
+
+END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
+
+CREATE_SIM_OBJECT(TraceCPU)
+{
+ return new TraceCPU(getInstanceName(),
+ (icache) ? icache->getInterface() : NULL,
+ (dcache) ? dcache->getInterface() : NULL,
+ inst_trace, data_trace, inst_ports, data_ports);
+}
+
+REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
+
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
new file mode 100644
index 000000000..13a204f4e
--- /dev/null
+++ b/cpu/trace/trace_cpu.hh
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a memory trace CPU object. Uses a memory trace to drive the
+ * provided memory hierarchy.
+ */
+
+#ifndef __TRACE_CPU_HH__
+#define __TRACE_CPU_HH__
+
+#include <string>
+
+#include "cpu/base_cpu.hh"
+#include "mem/mem_req.hh" // for MemReqPtr
+#include "sim/eventq.hh" // for Event
+
+// Forward declaration.
+class MemInterface;
+class MemTraceReader;
+
+/**
+ * A cpu object for running memory traces through a memory hierarchy.
+ */
+class TraceCPU : public BaseCPU
+{
+ /** Interface for instruction trace requests, if any. */
+ MemInterface *icacheInterface;
+ /** Interface for data trace requests, if any. */
+ MemInterface *dcacheInterface;
+
+ /** Instruction reference trace. */
+ MemTraceReader *instTrace;
+ /** Data reference trace. */
+ MemTraceReader *dataTrace;
+
+ /** Number of Icache read ports. */
+ int icachePorts;
+ /** Number of Dcache read/write ports. */
+ int dcachePorts;
+
+ /** Number of outstanding requests. */
+ int outstandingRequests;
+
+ /** Cycle of the next instruction request, 0 if not available. */
+ Tick nextInstCycle;
+ /** Cycle of the next data request, 0 if not available. */
+ Tick nextDataCycle;
+
+ /** Next instruction request. */
+ MemReqPtr nextInstReq;
+ /** Next data request. */
+ MemReqPtr nextDataReq;
+
+ /**
+ * Event to call the TraceCPU::tick
+ */
+ class TickEvent : public Event
+ {
+ private:
+ /** The associated CPU */
+ TraceCPU *cpu;
+
+ public:
+ /**
+ * Construct this event;
+ */
+ TickEvent(TraceCPU *c);
+
+ /**
+ * Call the tick function.
+ */
+ void process();
+
+ /**
+ * Return a string description of this event.
+ */
+ const char *description();
+ };
+
+ TickEvent tickEvent;
+
+ public:
+ /**
+ * Construct a TraceCPU object.
+ */
+ TraceCPU(const std::string &name,
+ MemInterface *icache_interface,
+ MemInterface *dcache_interface,
+ MemTraceReader *inst_trace,
+ MemTraceReader *data_trace,
+ int icache_ports,
+ int dcache_ports);
+
+ /**
+ * Perform all the accesses for one cycle.
+ */
+ void tick();
+
+ /**
+ * Handle a completed memory request.
+ */
+ void completeRequest(MemReqPtr &req);
+};
+
+class TraceCompleteEvent : public Event
+{
+ MemReqPtr req;
+ TraceCPU *tester;
+
+ public:
+
+ TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester)
+ : Event(&mainEventQueue), req(_req), tester(_tester)
+ {
+ setFlags(AutoDelete);
+ }
+
+ void process();
+
+ virtual const char *description();
+};
+
+#endif //__TRACE_CPU_HH__
+