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authorNathan Binkert <binkertn@umich.edu>2003-11-05 17:57:41 -0500
committerNathan Binkert <binkertn@umich.edu>2003-11-05 17:57:41 -0500
commit9471a4d20ffa98ae3f83edbe8cad1d282ab328af (patch)
tree08d0bd7401c1994b8688739df8f965b1326a65be /cpu
parent74fd8b1ad106c98e08bc433a6cc63a3c6cf564df (diff)
downloadgem5-9471a4d20ffa98ae3f83edbe8cad1d282ab328af.tar.xz
Fix stats reset
make SIGUSR2 dump and reset stats Make resetting time work base/statistics.cc: Fix statistics reset so that it works again, and correctly reset bins as well. (The old code wouldn't reset if you didn't have any bins, and then would actually only reset the first bin) cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: convert idleCycles/idleFraction into a single Average stat to make reset work more simply sim/main.cc: handle SIGUSR2 to dump and reset stats (SIGUSR1 only dumps them) sim/sim_time.cc: sim/sim_time.hh: Add support for resetting the time --HG-- extra : convert_revision : ea43e03c50c0a4bb826dc0842a8c4fa1a9289e0a
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.cc9
-rw-r--r--cpu/simple_cpu/simple_cpu.hh8
2 files changed, 3 insertions, 14 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 814902390..550b6c64f 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -160,7 +160,6 @@ SimpleCPU::SimpleCPU(const string &_name, Process *_process,
numInst = 0;
numLoad = 0;
- last_idle = 0;
lastIcacheStall = 0;
lastDcacheStall = 0;
@@ -171,7 +170,6 @@ SimpleCPU::~SimpleCPU()
{
}
-
void
SimpleCPU::switchOut()
{
@@ -229,11 +227,6 @@ SimpleCPU::regStats()
.desc("Number of memory references")
;
- idleCycles
- .name(name() + ".idle_cycles")
- .desc("Number of idle cycles")
- ;
-
idleFraction
.name(name() + ".idle_fraction")
.desc("Percentage of idle cycles")
@@ -251,8 +244,6 @@ SimpleCPU::regStats()
.prereq(dcacheStallCycles)
;
- idleFraction = idleCycles / simTicks;
-
numInsts = Statistics::scalar(numInst);
simInsts += numInsts;
}
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 6ad831218..d69d4e8de 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -207,7 +207,7 @@ class SimpleCPU : public BaseCPU
case Idle:
assert(old_status == Running);
- last_idle = curTick;
+ idleFraction++;
if (tickEvent.scheduled())
tickEvent.squash();
break;
@@ -217,7 +217,7 @@ class SimpleCPU : public BaseCPU
old_status == DcacheMissStall ||
old_status == IcacheMissComplete);
if (old_status == Idle && curTick != 0)
- idleCycles += curTick - last_idle;
+ idleFraction--;
if (tickEvent.squashed())
tickEvent.reschedule(curTick + 1);
@@ -244,9 +244,7 @@ class SimpleCPU : public BaseCPU
Counter numLoad;
// number of idle cycles
- Statistics::Scalar<> idleCycles;
- Statistics::Formula idleFraction;
- Counter last_idle;
+ Statistics::Average<> idleFraction;
// number of cycles stalled for I-cache misses
Statistics::Scalar<> icacheStallCycles;