Move to a model with a unified request object.

Constructor takes a bool to signify that it is either a cpu_request or not a cpu_request.
When accedding variables of a cpu_request it asserts that it is a cpu_request.
It also asserts that a value being read has been written at some point in time prior (not gaurnteeing it is up to date, but it was at least written before read).

There is also a isCpuReq() function to determine if this is a cpu_request.  It should be called before accesing a cpu_request only variable.

SConscript:
    Add compilation support for request.cc
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/io_device.cc:
mem/page_table.cc:
mem/page_table.hh:
mem/port.cc:
    Update for unified request object and accessor functions.
mem/request.hh:
    Remove CpuRequest, make it a unified object.  Make variables private with accessor functions.

    May want to move things from .cc file into header (usually a assert() and either returning a value, or writting two).

--HG--
extra : convert_revision : f1e45cc490dadc7a418634539b03c3e72684a6e3

4 files changed, 45 insertions, 45 deletions

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index c74feec68..eb5d712b9 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -241,17 +241,17 @@ class CPUExecContext
     int getInstAsid() { return regs.instAsid(); }
     int getDataAsid() { return regs.dataAsid(); }
 
-    Fault translateInstReq(CpuRequestPtr &req)
+    Fault translateInstReq(RequestPtr &req)
     {
         return itb->translate(req, proxy);
     }
 
-    Fault translateDataReadReq(CpuRequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req)
     {
         return dtb->translate(req, proxy, false);
     }
 
-    Fault translateDataWriteReq(CpuRequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req)
     {
         return dtb->translate(req, proxy, true);
     }
@@ -273,17 +273,17 @@ class CPUExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault translateInstReq(CpuRequestPtr &req)
+    Fault translateInstReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
 
-    Fault translateDataReadReq(CpuRequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
 
-    Fault translateDataWriteReq(CpuRequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
@@ -292,7 +292,7 @@ class CPUExecContext
 
 /*
     template <class T>
-    Fault read(CpuRequestPtr &req, T &data)
+    Fault read(RequestPtr &req, T &data)
     {
 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
@@ -308,7 +308,7 @@ class CPUExecContext
     }
 
     template <class T>
-    Fault write(CpuRequestPtr &req, T &data)
+    Fault write(RequestPtr &req, T &data)
     {
 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
@@ -369,7 +369,7 @@ class CPUExecContext
         inst = new_inst;
     }
 
-    Fault instRead(CpuRequestPtr &req)
+    Fault instRead(RequestPtr &req)
     {
         panic("instRead not implemented");
         // return funcPhysMem->read(req, inst);
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index dd3d2cba1..9404b126b 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -152,11 +152,11 @@ class ExecContext
     virtual int getInstAsid() = 0;
     virtual int getDataAsid() = 0;
 
-    virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
+    virtual Fault translateInstReq(RequestPtr &req) = 0;
 
-    virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
+    virtual Fault translateDataReadReq(RequestPtr &req) = 0;
 
-    virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
+    virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
 
     // Also somewhat obnoxious.  Really only used for the TLB fault.
     // However, may be quite useful in SPARC.
@@ -327,13 +327,13 @@ class ProxyExecContext : public ExecContext
     int getInstAsid() { return actualXC->getInstAsid(); }
     int getDataAsid() { return actualXC->getDataAsid(); }
 
-    Fault translateInstReq(CpuRequestPtr &req)
+    Fault translateInstReq(RequestPtr &req)
     { return actualXC->translateInstReq(req); }
 
-    Fault translateDataReadReq(CpuRequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req)
     { return actualXC->translateDataReadReq(req); }
 
-    Fault translateDataWriteReq(CpuRequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req)
     { return actualXC->translateDataWriteReq(req); }
 
     // @todo: Do I need this?
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 88c99c566..261ed8302 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -175,24 +175,24 @@ SimpleCPU::SimpleCPU(Params *p)
     xcProxy = cpuXC->getProxy();
 
 #if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
-    ifetch_req = new CpuRequest;
-    ifetch_req->asid = 0;
-    ifetch_req->size = sizeof(MachInst);
+    ifetch_req = new Request(true);
+    ifetch_req->setAsid(0);
+    ifetch_req->setSize(sizeof(MachInst));
     ifetch_pkt = new Packet;
     ifetch_pkt->cmd = Read;
     ifetch_pkt->data = (uint8_t *)&inst;
     ifetch_pkt->req = ifetch_req;
     ifetch_pkt->size = sizeof(MachInst);
 
-    data_read_req = new CpuRequest;
-    data_read_req->asid = 0;
+    data_read_req = new Request(true);
+    data_read_req->setAsid(0);
     data_read_pkt = new Packet;
     data_read_pkt->cmd = Read;
     data_read_pkt->data = new uint8_t[8];
     data_read_pkt->req = data_read_req;
 
-    data_write_req = new CpuRequest;
-    data_write_req->asid = 0;
+    data_write_req = new Request(true);
+    data_write_req->setAsid(0);
     data_write_pkt = new Packet;
     data_write_pkt->cmd = Write;
     data_write_pkt->req = data_write_req;
@@ -493,13 +493,13 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
 //    memReq->reset(addr, sizeof(T), flags);
 
 #if SIMPLE_CPU_MEM_TIMING
-    CpuRequest *data_read_req = new CpuRequest;
+    CpuRequest *data_read_req = new Request(true);
 #endif
 
-    data_read_req->vaddr = addr;
-    data_read_req->size = sizeof(T);
-    data_read_req->flags = flags;
-    data_read_req->time = curTick;
+    data_read_req->setVaddr(addr);
+    data_read_req->setSize(sizeof(T));
+    data_read_req->setFlags(flags);
+    data_read_req->setTime(curTick);
 
     // translate to physical address
     Fault fault = cpuXC->translateDataReadReq(data_read_req);
@@ -512,7 +512,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         data_read_pkt->req = data_read_req;
         data_read_pkt->data = new uint8_t[8];
 #endif
-        data_read_pkt->addr = data_read_req->paddr;
+        data_read_pkt->addr = data_read_req->getPaddr();
         data_read_pkt->size = sizeof(T);
 
         sendDcacheRequest(data_read_pkt);
@@ -559,7 +559,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 */
     // This will need a new way to tell if it has a dcache attached.
-    if (data_read_req->flags & UNCACHEABLE)
+    if (data_read_req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Read");
 
     return fault;
@@ -612,10 +612,10 @@ template <class T>
 Fault
 SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
-    data_write_req->vaddr = addr;
-    data_write_req->time = curTick;
-    data_write_req->size = sizeof(T);
-    data_write_req->flags = flags;
+    data_write_req->setVaddr(addr);
+    data_write_req->setTime(curTick);
+    data_write_req->setSize(sizeof(T));
+    data_write_req->setFlags(flags);
 
     // translate to physical address
     Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -630,7 +630,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 #else
         data_write_pkt->data = (uint8_t *)&data;
 #endif
-        data_write_pkt->addr = data_write_req->paddr;
+        data_write_pkt->addr = data_write_req->getPaddr();
         data_write_pkt->size = sizeof(T);
 
         sendDcacheRequest(data_write_pkt);
@@ -664,7 +664,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         *res = data_write_pkt->result;
 
     // This will need a new way to tell if it's hooked up to a cache or not.
-    if (data_write_req->flags & UNCACHEABLE)
+    if (data_write_req->getFlags() & UNCACHEABLE)
         recordEvent("Uncached Write");
 
     // If the write needs to have a fault on the access, consider calling
@@ -973,11 +973,11 @@ SimpleCPU::tick()
 
 #if SIMPLE_CPU_MEM_TIMING
         CpuRequest *ifetch_req = new CpuRequest();
-        ifetch_req->size = sizeof(MachInst);
+        ifetch_req->setSize(sizeof(MachInst));
 #endif
 
-        ifetch_req->vaddr = cpuXC->readPC() & ~3;
-        ifetch_req->time = curTick;
+        ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+        ifetch_req->setTime(curTick);
 
 /*	memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
                      IFETCH_FLAGS(xc->regs.pc));
@@ -993,7 +993,7 @@ SimpleCPU::tick()
             ifetch_pkt->req = ifetch_req;
             ifetch_pkt->size = sizeof(MachInst);
 #endif
-            ifetch_pkt->addr = ifetch_req->paddr;
+            ifetch_pkt->addr = ifetch_req->getPaddr();
 
             sendIcacheRequest(ifetch_pkt);
 #if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 43287a33b..11137b6e6 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -210,12 +210,12 @@ class SimpleCPU : public BaseCPU
 #if SIMPLE_CPU_MEM_TIMING
     Packet *retry_pkt;
 #elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
-    CpuRequest *ifetch_req;
-    Packet     *ifetch_pkt;
-    CpuRequest *data_read_req;
-    Packet     *data_read_pkt;
-    CpuRequest *data_write_req;
-    Packet     *data_write_pkt;
+    Request *ifetch_req;
+    Packet  *ifetch_pkt;
+    Request *data_read_req;
+    Packet  *data_read_pkt;
+    Request *data_write_req;
+    Packet  *data_write_pkt;
 #endif
 
     // Pointer to the sampler that is telling us to switchover.