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authorKorey Sewell <ksewell@umich.edu>2006-02-18 14:38:23 -0500
committerKorey Sewell <ksewell@umich.edu>2006-02-18 14:38:23 -0500
commitbd175809286e8da64176da977aeb27fc6ff6d272 (patch)
treed6c9d1fc0388e730a73408c483789ef88fa51b0e /cpu
parent159e3345314b921f05f808ace06d62adf79f095a (diff)
downloadgem5-bd175809286e8da64176da977aeb27fc6ff6d272.tar.xz
changes from mergedmem
arch/mips/isa/formats/branch.isa: add branch_likely member functions cpu/base.hh: cpu/exec_context.hh: cpu/static_inst.hh: change from mergedmem --HG-- extra : convert_revision : d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
Diffstat (limited to 'cpu')
-rw-r--r--cpu/base.hh4
-rw-r--r--cpu/exec_context.hh40
-rw-r--r--cpu/static_inst.hh10
3 files changed, 32 insertions, 22 deletions
diff --git a/cpu/base.hh b/cpu/base.hh
index 2bd1210d8..09a73ab16 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -36,7 +36,7 @@
#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
-#include "arch/isa_traits.hh"
+#include "targetarch/isa_traits.hh"
#if FULL_SYSTEM
class System;
@@ -140,6 +140,8 @@ class BaseCPU : public SimObject
virtual void startup();
virtual void regStats();
+ virtual void activateWhenReady(int tid) {};
+
void registerExecContexts();
/// Prepare for another CPU to take over execution. When it is
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 7e195af23..845f9264b 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -80,7 +80,7 @@ class ExecContext
Active,
/// Temporarily inactive. Entered while waiting for
- /// synchronization, etc.
+ /// initialization,synchronization, etc.
Suspended,
/// Permanently shut down. Entered when target executes
@@ -95,6 +95,8 @@ class ExecContext
public:
Status status() const { return _status; }
+ void setStatus(Status newStatus) { _status = newStatus; }
+
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
void activate(int delay = 1);
@@ -206,17 +208,17 @@ class ExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@@ -231,7 +233,7 @@ class ExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault * dummyTranslation(MemReqPtr &req)
+ Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -240,17 +242,17 @@ class ExecContext
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
- return NoFault;
+ return No_Fault;
}
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -258,7 +260,7 @@ class ExecContext
#endif
template <class T>
- Fault * read(MemReqPtr &req, T &data)
+ Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -268,14 +270,14 @@ class ExecContext
}
#endif
- Fault * error;
+ Fault error;
error = mem->read(req, data);
data = LittleEndianGuest::gtoh(data);
return error;
}
template <class T>
- Fault * write(MemReqPtr &req, T &data)
+ Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -301,7 +303,7 @@ class ExecContext
<< "on cpu " << req->xc->cpu_id
<< std::endl;
}
- return NoFault;
+ return No_Fault;
}
else req->xc->storeCondFailures = 0;
}
@@ -333,7 +335,7 @@ class ExecContext
inst = new_inst;
}
- Fault * instRead(MemReqPtr &req)
+ Fault instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
@@ -412,13 +414,13 @@ class ExecContext
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
- Fault * hwrei();
+ Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault * fault);
+ void ev5_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif
@@ -428,7 +430,7 @@ class ExecContext
* @todo How to do this properly so it's dependent upon ISA only?
*/
- void trap(Fault * fault);
+ void trap(Fault fault);
#if !FULL_SYSTEM
IntReg getSyscallArg(int i)
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 24997eadc..c574173c2 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -36,7 +36,7 @@
#include "base/refcnt.hh"
#include "encumbered/cpu/full/op_class.hh"
#include "sim/host.hh"
-#include "arch/isa_traits.hh"
+#include "targetarch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;
@@ -113,6 +113,8 @@ class StaticInstBase : public RefCounted
IsSerializing, ///< Serializes pipeline: won't execute until all
/// older instructions have committed.
+ IsSerializeBefore,
+ IsSerializeAfter,
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
@@ -196,7 +198,11 @@ class StaticInstBase : public RefCounted
bool isUncondCtrl() const { return flags[IsUncondControl]; }
bool isThreadSync() const { return flags[IsThreadSync]; }
- bool isSerializing() const { return flags[IsSerializing]; }
+ bool isSerializing() const { return flags[IsSerializing] ||
+ flags[IsSerializeBefore] ||
+ flags[IsSerializeAfter]; }
+ bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
+ bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
bool isMemBarrier() const { return flags[IsMemBarrier]; }
bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
bool isNonSpeculative() const { return flags[IsNonSpeculative]; }