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authorSteve Reinhardt <stever@eecs.umich.edu>2004-06-15 10:48:08 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2004-06-15 10:48:08 -0700
commitd53c6c168afa7eafdf8c4fa10a10f835db25e3da (patch)
treec001ef81c09fb8e52afb64df5b2a5a231fe7a352 /cpu
parent7b24ae00dc2b3f503a15c28a7728cfc9a3e9299f (diff)
downloadgem5-d53c6c168afa7eafdf8c4fa10a10f835db25e3da.tar.xz
Get software prefetching to work in full-system mode.
Mostly a matter of keeping prefetches to invalid addrs from messing up VM IPRs. Also discovered that wh64s were not being treated as prefetches, when they really should be (for the most part, anyway). arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). - Add NO_FAULT MemReq flag to indicate references that should not cause page faults (i.e., prefetches). arch/alpha/ev5.cc: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). - Add Fault trace flag. arch/alpha/isa_desc: - Add NO_FAULT MemReq flag to indicate references that should not cause page faults (i.e., prefetches). - Mark wh64 as a "data prefetch" instruction so it gets controlled properly by the FullCPU data prefetch control switch. - Align wh64 EA in decoder so issue stage doesn't need to worry about it. arch/alpha/isa_traits.hh: - Get rid of intrlock flag for locking VM fault regs (a la EV5); instead, just don't update regs on VPTE loads (a la EV6). base/traceflags.py: - Add Fault trace flag. cpu/simple_cpu/simple_cpu.hh: - Pass MemReq flags to writeHint() operation. cpu/static_inst.hh: Update comment re: prefetches. --HG-- extra : convert_revision : 62e466b0f4c0ff9961796270fa2e371ec24bcbb6
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple_cpu/simple_cpu.hh2
-rw-r--r--cpu/static_inst.hh3
2 files changed, 2 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index 1c6b18d03..545c753f0 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -253,7 +253,7 @@ class SimpleCPU : public BaseCPU
// need to do this...
}
- void writeHint(Addr addr, int size)
+ void writeHint(Addr addr, int size, unsigned flags)
{
// need to do this...
}
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 3eeefb675..68c30df2f 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -72,8 +72,7 @@ class StaticInstBase : public RefCounted
/// unconditional branches, memory barriers) or both (e.g., an
/// FP/int conversion).
/// - If IsMemRef is set, then exactly one of IsLoad or IsStore
- /// will be set. Prefetches are marked as IsLoad, even if they
- /// prefetch exclusive copies.
+ /// will be set.
/// - If IsControl is set, then exactly one of IsDirectControl or
/// IsIndirect Control will be set, and exactly one of
/// IsCondControl or IsUncondControl will be set.