summaryrefslogtreecommitdiff
path: root/cpu
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-02-19 03:04:44 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-19 03:04:44 -0500
commited25d326174f8086a8224ecb9e798410db14cddb (patch)
tree8ec20b844bb3b19940c304070251720c6998f1bd /cpu
parent0e4a80df1a471671b6ef7003e29124b6835ade42 (diff)
downloadgem5-ed25d326174f8086a8224ecb9e798410db14cddb.tar.xz
Remade some changes which were undone
cpu/base.hh: cpu/static_inst.hh: Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh cpu/exec_context.hh: Changed Fault back to Fault * --HG-- extra : convert_revision : 410f2e2472f8aa5bf92619a5defdf85f689a5597
Diffstat (limited to 'cpu')
-rw-r--r--cpu/base.hh2
-rw-r--r--cpu/exec_context.hh36
-rw-r--r--cpu/static_inst.hh2
3 files changed, 20 insertions, 20 deletions
diff --git a/cpu/base.hh b/cpu/base.hh
index 82a47bf4c..311b50f7f 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -36,7 +36,7 @@
#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
#if FULL_SYSTEM
class System;
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index f11d69273..3c6bad34d 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -214,17 +214,17 @@ class ExecContext
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault translateInstReq(MemReqPtr &req)
+ Fault * translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault * translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault * translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
@@ -239,7 +239,7 @@ class ExecContext
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault dummyTranslation(MemReqPtr &req)
+ Fault * dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -248,17 +248,17 @@ class ExecContext
// put the asid in the upper 16 bits of the paddr
req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
- return No_Fault;
+ return NoFault;
}
- Fault translateInstReq(MemReqPtr &req)
+ Fault * translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault translateDataReadReq(MemReqPtr &req)
+ Fault * translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault translateDataWriteReq(MemReqPtr &req)
+ Fault * translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -266,7 +266,7 @@ class ExecContext
#endif
template <class T>
- Fault read(MemReqPtr &req, T &data)
+ Fault * read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -276,14 +276,14 @@ class ExecContext
}
#endif
- Fault error;
+ Fault * error;
error = mem->read(req, data);
data = LittleEndianGuest::gtoh(data);
return error;
}
template <class T>
- Fault write(MemReqPtr &req, T &data)
+ Fault * write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -309,7 +309,7 @@ class ExecContext
<< "on cpu " << req->xc->cpu_id
<< std::endl;
}
- return No_Fault;
+ return NoFault;
}
else req->xc->storeCondFailures = 0;
}
@@ -341,7 +341,7 @@ class ExecContext
inst = new_inst;
}
- Fault instRead(MemReqPtr &req)
+ Fault * instRead(MemReqPtr &req)
{
return mem->read(req, inst);
}
@@ -420,13 +420,13 @@ class ExecContext
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault &fault);
- Fault setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault * &fault);
+ Fault * setIpr(int idx, uint64_t val);
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
- Fault hwrei();
+ Fault * hwrei();
bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
- void ev5_trap(Fault fault);
+ void ev5_trap(Fault * fault);
bool simPalCheck(int palFunc);
#endif
@@ -436,7 +436,7 @@ class ExecContext
* @todo How to do this properly so it's dependent upon ISA only?
*/
- void trap(Fault fault);
+ void trap(Fault * fault);
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 333a6f1ca..1ff14df08 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -36,7 +36,7 @@
#include "base/refcnt.hh"
#include "encumbered/cpu/full/op_class.hh"
#include "sim/host.hh"
-#include "targetarch/isa_traits.hh"
+#include "arch/isa_traits.hh"
// forward declarations
struct AlphaSimpleImpl;