Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

15 files changed, 184 insertions, 183 deletions

diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index d921bd148..59a12f2d0 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -113,7 +113,7 @@ BaseDynInst<Impl>::initVars()
     asid = 0;
 
     // Initialize the fault to be unimplemented opcode.
-    fault = Unimplemented_Opcode_Fault;
+    fault = UnimplementedOpcodeFault;
 
     ++instcount;
 
@@ -142,12 +142,12 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
     req->asid = asid;
 
     // Prefetches never cause faults.
-    fault = No_Fault;
+    fault = NoFault;
 
     // note this is a local, not BaseDynInst::fault
-    Fault trans_fault = xc->translateDataReadReq(req);
+    Fault * trans_fault = xc->translateDataReadReq(req);
 
-    if (trans_fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // It's a valid address to cacheable space.  Record key MemReq
         // parameters so we can generate another one just like it for
         // the timing access without calling translate() again (which
@@ -188,7 +188,7 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 
     fault = xc->translateDataWriteReq(req);
 
-    if (fault == No_Fault && !(req->flags & UNCACHEABLE)) {
+    if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
         // Record key MemReq parameters so we can generate another one
         // just like it for the timing access without calling translate()
         // again (which might mess up the TLB).
@@ -208,16 +208,16 @@ BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
  * @todo Need to find a way to get the cache block size here.
  */
 template <class Impl>
-Fault
+Fault *
 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 {
     MemReqPtr req = new MemReq(src, xc, 64);
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(req);
+    Fault * fault = xc->translateDataReadReq(req);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         xc->copySrcAddr = src;
         xc->copySrcPhysAddr = req->paddr;
     } else {
@@ -231,7 +231,7 @@ BaseDynInst<Impl>::copySrcTranslate(Addr src)
  * @todo Need to find a way to get the cache block size here.
  */
 template <class Impl>
-Fault
+Fault *
 BaseDynInst<Impl>::copy(Addr dest)
 {
     uint8_t data[64];
@@ -241,9 +241,9 @@ BaseDynInst<Impl>::copy(Addr dest)
     req->asid = asid;
 
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(req);
+    Fault * fault = xc->translateDataWriteReq(req);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         Addr dest_addr = req->paddr;
         // Need to read straight from memory since we have more than 8 bytes.
         req->paddr = xc->copySrcPhysAddr;
@@ -277,10 +277,10 @@ BaseDynInst<Impl>::dump(std::string &outstring)
 
 #if 0
 template <class Impl>
-Fault
+Fault *
 BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 {
-    Fault fault;
+    Fault * fault;
 
     // check alignments, even speculative this test should always pass
     if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
@@ -292,7 +292,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 #if 0
         panic("unaligned access. Cycle = %n", curTick);
 #endif
-        return No_Fault;
+        return NoFault;
     }
 
     MemReqPtr req = new MemReq(addr, thread, nbytes);
@@ -303,7 +303,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 
       case Write:
         fault = spec_mem->write(req, (uint8_t *)p);
-        if (fault != No_Fault)
+        if (fault != NoFault)
             break;
 
         specMemWrite = true;
@@ -325,7 +325,7 @@ BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
         break;
 
       default:
-        fault = Machine_Check_Fault;
+        fault = MachineCheckFault;
         break;
     }
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index d29257a52..2c91db99c 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -89,16 +89,16 @@ class BaseDynInst : public FastAlloc, public RefCounted
     Trace::InstRecord *traceData;
 
     template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault * read(Addr addr, T &data, unsigned flags);
 
     template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
+    Fault * write(T data, Addr addr, unsigned flags,
                         uint64_t *res);
 
     void prefetch(Addr addr, unsigned flags);
     void writeHint(Addr addr, int size, unsigned flags);
-    Fault copySrcTranslate(Addr src);
-    Fault copy(Addr dest);
+    Fault * copySrcTranslate(Addr src);
+    Fault * copy(Addr dest);
 
     /** @todo: Consider making this private. */
   public:
@@ -154,7 +154,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
     ExecContext *xc;
 
     /** The kind of fault this instruction has generated. */
-    Fault fault;
+    Fault * fault;
 
     /** The effective virtual address (lds & stores only). */
     Addr effAddr;
@@ -225,7 +225,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
   public:
     void
-    trace_mem(Fault fault,      // last fault
+    trace_mem(Fault * fault,      // last fault
               MemCmd cmd,       // last command
               Addr addr,        // virtual address of access
               void *p,          // memory accessed
@@ -238,7 +238,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
     void dump(std::string &outstring);
 
     /** Returns the fault type. */
-    Fault getFault() { return fault; }
+    Fault * getFault() { return fault; }
 
     /** Checks whether or not this instruction has had its branch target
      *  calculated yet.  For now it is not utilized and is hacked to be
@@ -447,7 +447,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
 template<class Impl>
 template<class T>
-inline Fault
+inline Fault *
 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
 {
     MemReqPtr req = new MemReq(addr, xc, sizeof(T), flags);
@@ -472,7 +472,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     req->paddr = req->vaddr;
 #endif
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         fault = cpu->read(req, data, lqIdx);
     } else {
         // Return a fixed value to keep simulation deterministic even
@@ -490,7 +490,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
 
 template<class Impl>
 template<class T>
-inline Fault
+inline Fault *
 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     if (traceData) {
@@ -520,14 +520,14 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     req->paddr = req->vaddr;
 #endif
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         fault = cpu->write(req, data, sqIdx);
     }
 
     if (res) {
         // always return some result to keep misspeculated paths
         // (which will ignore faults) deterministic
-        *res = (fault == No_Fault) ? req->result : 0;
+        *res = (fault == NoFault) ? req->result : 0;
     }
 
     return fault;
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 9bed3ba47..e7facbebb 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -221,7 +221,7 @@ ExecContext::regStats(const string &name)
 }
 
 void
-ExecContext::trap(Fault fault)
+ExecContext::trap(Fault * fault)
 {
     //TheISA::trap(fault);    //One possible way to do it...
 
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 846be831a..7e195af23 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -206,17 +206,17 @@ class ExecContext
     int getInstAsid() { return regs.instAsid(); }
     int getDataAsid() { return regs.dataAsid(); }
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
@@ -231,7 +231,7 @@ class ExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault dummyTranslation(MemReqPtr &req)
+    Fault * dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -240,17 +240,17 @@ class ExecContext
         // put the asid in the upper 16 bits of the paddr
         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
-        return No_Fault;
+        return NoFault;
     }
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -258,7 +258,7 @@ class ExecContext
 #endif
 
     template <class T>
-    Fault read(MemReqPtr &req, T &data)
+    Fault * read(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
@@ -268,14 +268,14 @@ class ExecContext
         }
 #endif
 
-        Fault error;
+        Fault * error;
         error = mem->read(req, data);
         data = LittleEndianGuest::gtoh(data);
         return error;
     }
 
     template <class T>
-    Fault write(MemReqPtr &req, T &data)
+    Fault * write(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 
@@ -301,7 +301,7 @@ class ExecContext
                                   << "on cpu " << req->xc->cpu_id
                                   << std::endl;
                     }
-                    return No_Fault;
+                    return NoFault;
                 }
                 else req->xc->storeCondFailures = 0;
             }
@@ -333,7 +333,7 @@ class ExecContext
         inst = new_inst;
     }
 
-    Fault instRead(MemReqPtr &req)
+    Fault * instRead(MemReqPtr &req)
     {
         return mem->read(req, inst);
     }
@@ -412,13 +412,13 @@ class ExecContext
     }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
+    uint64_t readIpr(int idx, Fault * &fault);
+    Fault * setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
     void setIntrFlag(int val) { regs.intrflag = val; }
-    Fault hwrei();
+    Fault * hwrei();
     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
-    void ev5_trap(Fault fault);
+    void ev5_trap(Fault * fault);
     bool simPalCheck(int palFunc);
 #endif
 
@@ -428,7 +428,7 @@ class ExecContext
      *  @todo How to do this properly so it's dependent upon ISA only?
      */
 
-    void trap(Fault fault);
+    void trap(Fault * fault);
 
 #if !FULL_SYSTEM
     IntReg getSyscallArg(int i)
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 1e1a72af0..606f9fa0a 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -62,23 +62,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 //    void clear_interrupt(int int_num, int index);
 //    void clear_interrupts();
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
 
 #else
-    Fault dummyTranslation(MemReqPtr &req)
+    Fault * dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -87,20 +87,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         // put the asid in the upper 16 bits of the paddr
         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
-        return No_Fault;
+        return NoFault;
     }
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -135,16 +135,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // look like.
 #if FULL_SYSTEM
     uint64_t *getIpr();
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
+    uint64_t readIpr(int idx, Fault * &fault);
+    Fault * setIpr(int idx, uint64_t val);
     int readIntrFlag();
     void setIntrFlag(int val);
-    Fault hwrei();
+    Fault * hwrei();
     bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
     bool inPalMode(uint64_t PC)
     { return AlphaISA::PcPAL(PC); }
 
-    void trap(Fault fault);
+    void trap(Fault * fault);
     bool simPalCheck(int palFunc);
 
     void processInterrupts();
@@ -197,7 +197,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     bool palShadowEnabled;
 
     // Not sure this is used anywhere.
-    void intr_post(RegFile *regs, Fault fault, Addr pc);
+    void intr_post(RegFile *regs, Fault * fault, Addr pc);
     // Actually used within exec files.  Implement properly.
     void swapPALShadow(bool use_shadow);
     // Called by CPU constructor.  Can implement as I please.
@@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 
     template <class T>
-    Fault read(MemReqPtr &req, T &data)
+    Fault * read(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
@@ -220,20 +220,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
         }
 #endif
 
-        Fault error;
+        Fault * error;
         error = this->mem->read(req, data);
         data = gtoh(data);
         return error;
     }
 
     template <class T>
-    Fault read(MemReqPtr &req, T &data, int load_idx)
+    Fault * read(MemReqPtr &req, T &data, int load_idx)
     {
         return this->iew.ldstQueue.read(req, data, load_idx);
     }
 
     template <class T>
-    Fault write(MemReqPtr &req, T &data)
+    Fault * write(MemReqPtr &req, T &data)
     {
 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 
@@ -259,7 +259,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
                                   << "on cpu " << this->cpu_id
                                   << std::endl;
                     }
-                    return No_Fault;
+                    return NoFault;
                 }
                 else req->xc->storeCondFailures = 0;
             }
@@ -283,7 +283,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     }
 
     template <class T>
-    Fault write(MemReqPtr &req, T &data, int store_idx)
+    Fault * write(MemReqPtr &req, T &data, int store_idx)
     {
         return this->iew.ldstQueue.write(req, data, store_idx);
     }
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 3b16975a9..408676331 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
 
 template <class Impl>
 uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
+AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
 {
     return this->regFile.readIpr(idx, fault);
 }
 
 template <class Impl>
-Fault
+Fault *
 AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
 {
     return this->regFile.setIpr(idx, val);
@@ -274,13 +274,13 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
 
 // Can force commit stage to squash and stuff.
 template <class Impl>
-Fault
+Fault *
 AlphaFullCPU<Impl>::hwrei()
 {
     uint64_t *ipr = getIpr();
 
     if (!inPalMode())
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei()
     this->checkInterrupts = true;
 
     // FIXME: XXX check for interrupts? XXX
-    return No_Fault;
+    return NoFault;
 }
 
 template <class Impl>
@@ -323,28 +323,28 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
 // stage.
 template <class Impl>
 void
-AlphaFullCPU<Impl>::trap(Fault fault)
+AlphaFullCPU<Impl>::trap(Fault * fault)
 {
     // Keep in mind that a trap may be initiated by fetch if there's a TLB
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
-    this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
+    this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
 
 //    kernelStats.fault(fault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
     typename AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
-    if (fault != Interrupt_Fault || !inPalMode(PC))
+    if (fault != InterruptFault || !inPalMode(PC))
         ipr[AlphaISA::IPR_EXC_ADDR] = PC;
 
-    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+    if (fault == PalFault || fault == ArithmeticFault /* ||
+        fault == InterruptFault && !PC_PAL(regs.pc) */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
     }
@@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
         swapPALShadow(true);
 
     this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
-                         AlphaISA::fault_addr[fault] );
+                         AlphaISA::fault_addr(fault) );
     this->regFile.setNextPC(PC + sizeof(MachInst));
 }
 
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index bb90bf21a..77dcbaf74 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
 
     /** Executes the instruction.*/
-    Fault execute()
+    Fault * execute()
     {
         return this->fault = this->staticInst->execute(this, this->traceData);
     }
@@ -87,13 +87,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
     void setFpcr(uint64_t val);
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
-    Fault hwrei();
+    uint64_t readIpr(int idx, Fault * &fault);
+    Fault * setIpr(int idx, uint64_t val);
+    Fault * hwrei();
     int readIntrFlag();
     void setIntrFlag(int val);
     bool inPalMode();
-    void trap(Fault fault);
+    void trap(Fault * fault);
     bool simPalCheck(int palFunc);
 #else
     void syscall();
@@ -220,12 +220,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
     }
 
   public:
-    Fault calcEA()
+    Fault * calcEA()
     {
         return this->staticInst->eaCompInst()->execute(this, this->traceData);
     }
 
-    Fault memAccess()
+    Fault * memAccess()
     {
         return this->staticInst->memAccInst()->execute(this, this->traceData);
     }
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index d1ebb812d..b20af48cd 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
 #if FULL_SYSTEM
 template <class Impl>
 uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
+AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
 {
     return this->cpu->readIpr(idx, fault);
 }
 
 template <class Impl>
-Fault
+Fault *
 AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
 {
     return this->cpu->setIpr(idx, val);
 }
 
 template <class Impl>
-Fault
+Fault *
 AlphaDynInst<Impl>::hwrei()
 {
     return this->cpu->hwrei();
@@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
 
 template <class Impl>
 void
-AlphaDynInst<Impl>::trap(Fault fault)
+AlphaDynInst<Impl>::trap(Fault * fault)
 {
     this->cpu->trap(fault);
 }
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index dc0986772..540f16b78 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -393,9 +393,9 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
     }
 
     // Check if the instruction caused a fault.  If so, trap.
-    Fault inst_fault = head_inst->getFault();
+    Fault * inst_fault = head_inst->getFault();
 
-    if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
+    if (inst_fault != NoFault && inst_fault != FakeMemFault) {
         if (!head_inst->isNop()) {
 #if FULL_SYSTEM
             cpu->trap(inst_fault);
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 24e445f0b..5443d274e 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -123,7 +123,7 @@ class SimpleFetch
      * @param fetch_PC The PC address that is being fetched from.
      * @return Any fault that occured.
      */
-    Fault fetchCacheLine(Addr fetch_PC);
+    Fault * fetchCacheLine(Addr fetch_PC);
 
     inline void doSquash(const Addr &new_PC);
 
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index cd1ed1351..e8d333ed4 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
 }
 
 template <class Impl>
-Fault
+Fault *
 SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
 {
     // Check if the instruction exists within the cache.
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
     unsigned flags = 0;
 #endif // FULL_SYSTEM
 
-    Fault fault = No_Fault;
+    Fault * fault = NoFault;
 
     // Align the fetch PC so it's at the start of a cache block.
     fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -258,7 +258,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
 
     // If translation was successful, attempt to read the first
     // instruction.
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
         fault = cpu->mem->read(memReq, cacheData);
         // This read may change when the mem interface changes.
@@ -268,7 +268,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
 
     // Now do the timing access to see whether or not the instruction
     // exists within the cache.
-    if (icacheInterface && fault == No_Fault) {
+    if (icacheInterface && fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Doing timing memory access.\n");
         memReq->completionEvent = NULL;
 
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
     Addr fetch_PC = cpu->readPC();
 
     // Fault code for memory access.
-    Fault fault = No_Fault;
+    Fault * fault = NoFault;
 
     // If returning from the delay of a cache miss, then update the status
     // to running, otherwise do the cache access.  Possibly move this up
@@ -506,7 +506,7 @@ SimpleFetch<Impl>::fetch()
     unsigned offset = fetch_PC & cacheBlkMask;
     unsigned fetched;
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         // If the read of the first instruction was successful, then grab the
         // instructions from the rest of the cache line and put them into the
         // queue heading to decode.
@@ -582,7 +582,7 @@ SimpleFetch<Impl>::fetch()
     // Or might want to leave setting the PC to the main CPU, with fetch
     // only changing the nextPC (will require correct determination of
     // next PC).
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         DPRINTF(Fetch, "Fetch: Setting PC to %08p.\n", next_PC);
         cpu->setPC(next_PC);
         cpu->setNextPC(next_PC + instSize);
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 4d47b8f9c..5aafd5495 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -32,6 +32,7 @@
 // @todo: Destructor
 
 #include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/faults.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
@@ -211,8 +212,8 @@ class PhysRegFile
     }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault);
-    Fault setIpr(int idx, uint64_t val);
+    uint64_t readIpr(int idx, Fault * &fault);
+    Fault * setIpr(int idx, uint64_t val);
     InternalProcReg *getIpr() { return ipr; }
     int readIntrFlag() { return intrflag; }
     void setIntrFlag(int val) { intrflag = val; }
@@ -275,7 +276,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
 //the DynInst level.
 template <class Impl>
 uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
+PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
 {
     uint64_t retval = 0;    // return value, default 0
 
@@ -368,12 +369,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
       case ISA::IPR_DTB_IAP:
       case ISA::IPR_ITB_IA:
       case ISA::IPR_ITB_IAP:
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
     }
 
@@ -383,7 +384,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
 extern int break_ipl;
 
 template <class Impl>
-Fault
+Fault *
 PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
 {
     uint64_t old;
@@ -521,7 +522,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
       case ISA::IPR_ITB_PTE_TEMP:
       case ISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
       case ISA::IPR_HWINT_CLR:
       case ISA::IPR_SL_XMIT:
@@ -623,11 +624,11 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
     // no error...
-    return No_Fault;
+    return NoFault;
 }
 
 #endif // #if FULL_SYSTEM
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 5af77862a..21fe05b6a 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -286,17 +286,17 @@ class OoOCPU : public BaseCPU
     int getInstAsid() { return xc->regs.instAsid(); }
     int getDataAsid() { return xc->regs.dataAsid(); }
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return itb->translate(req);
     }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dtb->translate(req, false);
     }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dtb->translate(req, true);
     }
@@ -311,7 +311,7 @@ class OoOCPU : public BaseCPU
     int getInstAsid() { return xc->asid; }
     int getDataAsid() { return xc->asid; }
 
-    Fault dummyTranslation(MemReqPtr &req)
+    Fault * dummyTranslation(MemReqPtr &req)
     {
 #if 0
         assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -320,17 +320,17 @@ class OoOCPU : public BaseCPU
         // put the asid in the upper 16 bits of the paddr
         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
-        return No_Fault;
+        return NoFault;
     }
-    Fault translateInstReq(MemReqPtr &req)
+    Fault * translateInstReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault * translateDataReadReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault * translateDataWriteReq(MemReqPtr &req)
     {
         return dummyTranslation(req);
     }
@@ -338,10 +338,10 @@ class OoOCPU : public BaseCPU
 #endif
 
     template <class T>
-    Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
+    Fault * read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
 
     template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
+    Fault * write(T data, Addr addr, unsigned flags,
                 uint64_t *res, DynInstPtr inst);
 
     void prefetch(Addr addr, unsigned flags)
@@ -354,9 +354,9 @@ class OoOCPU : public BaseCPU
         // need to do this...
     }
 
-    Fault copySrcTranslate(Addr src);
+    Fault * copySrcTranslate(Addr src);
 
-    Fault copy(Addr dest);
+    Fault * copy(Addr dest);
 
   private:
     bool executeInst(DynInstPtr &inst);
@@ -369,7 +369,7 @@ class OoOCPU : public BaseCPU
 
     bool getOneInst();
 
-    Fault fetchCacheLine();
+    Fault * fetchCacheLine();
 
     InstSeqNum getAndIncrementInstSeq();
 
@@ -512,13 +512,13 @@ class OoOCPU : public BaseCPU
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
-    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
-    Fault hwrei() { return xc->hwrei(); }
+    uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
+    Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+    Fault * hwrei() { return xc->hwrei(); }
     int readIntrFlag() { return xc->readIntrFlag(); }
     void setIntrFlag(int val) { xc->setIntrFlag(val); }
     bool inPalMode() { return xc->inPalMode(); }
-    void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+    void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
     bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
 #else
     void syscall() { xc->syscall(); }
@@ -531,7 +531,7 @@ class OoOCPU : public BaseCPU
 // precise architected memory state accessor macros
 template <class Impl>
 template <class T>
-Fault
+Fault *
 OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
 {
     MemReqPtr readReq = new MemReq();
@@ -542,21 +542,21 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
     readReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address - This might be an ISA impl call
-    Fault fault = translateDataReadReq(readReq);
+    Fault * fault = translateDataReadReq(readReq);
 
     // do functional access
-    if (fault == No_Fault)
+    if (fault == NoFault)
         fault = xc->mem->read(readReq, data);
 #if 0
     if (traceData) {
         traceData->setAddr(addr);
-        if (fault == No_Fault)
+        if (fault == NoFault)
             traceData->setData(data);
     }
 #endif
 
     // if we have a cache, do cache access too
-    if (fault == No_Fault && dcacheInterface) {
+    if (fault == NoFault && dcacheInterface) {
         readReq->cmd = Read;
         readReq->completionEvent = NULL;
         readReq->time = curTick;
@@ -576,7 +576,7 @@ OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
 
 template <class Impl>
 template <class T>
-Fault
+Fault *
 OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
                     uint64_t *res, DynInstPtr inst)
 {
@@ -595,13 +595,13 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
     writeReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = translateDataWriteReq(writeReq);
+    Fault * fault = translateDataWriteReq(writeReq);
 
     // do functional access
-    if (fault == No_Fault)
+    if (fault == NoFault)
         fault = xc->write(writeReq, data);
 
-    if (fault == No_Fault && dcacheInterface) {
+    if (fault == NoFault && dcacheInterface) {
         writeReq->cmd = Write;
         memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
         writeReq->completionEvent = NULL;
@@ -614,7 +614,7 @@ OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
         }
     }
 
-    if (res && (fault == No_Fault))
+    if (res && (fault == NoFault))
         *res = writeReq->result;
 
     if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 70217f0bb..6aff94abd 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -312,7 +312,7 @@ change_thread_state(int thread_number, int activate, int priority)
 {
 }
 
-Fault
+Fault *
 SimpleCPU::copySrcTranslate(Addr src)
 {
     static bool no_warn = true;
@@ -332,11 +332,11 @@ SimpleCPU::copySrcTranslate(Addr src)
     memReq->reset(src & ~(blk_size - 1), blk_size);
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(memReq);
+    Fault * fault = xc->translateDataReadReq(memReq);
 
-    assert(fault != Alignment_Fault);
+    assert(fault != AlignmentFault);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         xc->copySrcAddr = src;
         xc->copySrcPhysAddr = memReq->paddr + offset;
     } else {
@@ -346,7 +346,7 @@ SimpleCPU::copySrcTranslate(Addr src)
     return fault;
 }
 
-Fault
+Fault *
 SimpleCPU::copy(Addr dest)
 {
     static bool no_warn = true;
@@ -367,11 +367,11 @@ SimpleCPU::copy(Addr dest)
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(memReq);
+    Fault * fault = xc->translateDataWriteReq(memReq);
 
-    assert(fault != Alignment_Fault);
+    assert(fault != AlignmentFault);
 
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
         Addr dest_addr = memReq->paddr + offset;
         // Need to read straight from memory since we have more than 8 bytes.
         memReq->paddr = xc->copySrcPhysAddr;
@@ -394,11 +394,11 @@ SimpleCPU::copy(Addr dest)
 
 // precise architected memory state accessor macros
 template <class T>
-Fault
+Fault *
 SimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
-        Fault fault = xc->read(memReq,data);
+        Fault * fault = xc->read(memReq,data);
 
         if (traceData) {
             traceData->setAddr(addr);
@@ -409,10 +409,10 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = xc->translateDataReadReq(memReq);
+    Fault * fault = xc->translateDataReadReq(memReq);
 
     // if we have a cache, do cache access too
-    if (fault == No_Fault && dcacheInterface) {
+    if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Read;
         memReq->completionEvent = NULL;
         memReq->time = curTick;
@@ -432,7 +432,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
             fault = xc->read(memReq, data);
 
         }
-    } else if(fault == No_Fault) {
+    } else if(fault == NoFault) {
         // do functional access
         fault = xc->read(memReq, data);
 
@@ -447,32 +447,32 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
-Fault
+Fault *
 SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 
 template
-Fault
+Fault *
 SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 
 template
-Fault
+Fault *
 SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 
 template
-Fault
+Fault *
 SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 
 #endif //DOXYGEN_SHOULD_SKIP_THIS
 
 template<>
-Fault
+Fault *
 SimpleCPU::read(Addr addr, double &data, unsigned flags)
 {
     return read(addr, *(uint64_t*)&data, flags);
 }
 
 template<>
-Fault
+Fault *
 SimpleCPU::read(Addr addr, float &data, unsigned flags)
 {
     return read(addr, *(uint32_t*)&data, flags);
@@ -480,7 +480,7 @@ SimpleCPU::read(Addr addr, float &data, unsigned flags)
 
 
 template<>
-Fault
+Fault *
 SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 {
     return read(addr, (uint32_t&)data, flags);
@@ -488,19 +488,19 @@ SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 
 
 template <class T>
-Fault
+Fault *
 SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     memReq->reset(addr, sizeof(T), flags);
 
     // translate to physical address
-    Fault fault = xc->translateDataWriteReq(memReq);
+    Fault * fault = xc->translateDataWriteReq(memReq);
 
     // do functional access
-    if (fault == No_Fault)
+    if (fault == NoFault)
         fault = xc->write(memReq, data);
 
-    if (fault == No_Fault && dcacheInterface) {
+    if (fault == NoFault && dcacheInterface) {
         memReq->cmd = Write;
         memcpy(memReq->data,(uint8_t *)&data,memReq->size);
         memReq->completionEvent = NULL;
@@ -519,7 +519,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         }
     }
 
-    if (res && (fault == No_Fault))
+    if (res && (fault == NoFault))
         *res = memReq->result;
 
     if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
@@ -531,32 +531,32 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 template
-Fault
+Fault *
 SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
 
 template
-Fault
+Fault *
 SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
 
 template
-Fault
+Fault *
 SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
 
 template
-Fault
+Fault *
 SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
 
 #endif //DOXYGEN_SHOULD_SKIP_THIS
 
 template<>
-Fault
+Fault *
 SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 {
     return write(*(uint64_t*)&data, addr, flags, res);
 }
 
 template<>
-Fault
+Fault *
 SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 {
     return write(*(uint32_t*)&data, addr, flags, res);
@@ -564,7 +564,7 @@ SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 
 
 template<>
-Fault
+Fault *
 SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 {
     return write((uint32_t)data, addr, flags, res);
@@ -638,7 +638,7 @@ SimpleCPU::tick()
 
     traceData = NULL;
 
-    Fault fault = No_Fault;
+    Fault * fault = NoFault;
 
 #if FULL_SYSTEM
     if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
@@ -675,7 +675,7 @@ SimpleCPU::tick()
         if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
             ipr[TheISA::IPR_ISR] = summary;
             ipr[TheISA::IPR_INTID] = ipl;
-            xc->ev5_trap(Interrupt_Fault);
+            xc->ev5_trap(InterruptFault);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                     ipr[TheISA::IPR_IPLR], ipl, summary);
@@ -713,10 +713,10 @@ SimpleCPU::tick()
 
         fault = xc->translateInstReq(memReq);
 
-        if (fault == No_Fault)
+        if (fault == NoFault)
             fault = xc->mem->read(memReq, inst);
 
-        if (icacheInterface && fault == No_Fault) {
+        if (icacheInterface && fault == NoFault) {
             memReq->completionEvent = NULL;
 
             memReq->time = curTick;
@@ -738,7 +738,7 @@ SimpleCPU::tick()
 
     // If we've got a valid instruction (i.e., no fault on instruction
     // fetch), then execute it.
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
 
         // keep an instruction count
         numInst++;
@@ -795,9 +795,9 @@ SimpleCPU::tick()
 
         traceFunctions(xc->regs.pc);
 
-    }	// if (fault == No_Fault)
+    }	// if (fault == NoFault)
 
-    if (fault != No_Fault) {
+    if (fault != NoFault) {
 #if FULL_SYSTEM
         xc->ev5_trap(fault);
 #else // !FULL_SYSTEM
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 0f7251237..e7a447117 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -234,10 +234,10 @@ class SimpleCPU : public BaseCPU
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
     template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault * read(Addr addr, T &data, unsigned flags);
 
     template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+    Fault * write(T data, Addr addr, unsigned flags, uint64_t *res);
 
     // These functions are only used in CPU models that split
     // effective address computation from the actual memory access.
@@ -254,9 +254,9 @@ class SimpleCPU : public BaseCPU
         // need to do this...
     }
 
-    Fault copySrcTranslate(Addr src);
+    Fault * copySrcTranslate(Addr src);
 
-    Fault copy(Addr dest);
+    Fault * copy(Addr dest);
 
     // The register accessor methods provide the index of the
     // instruction's operand (e.g., 0 or 1), not the architectural
@@ -325,13 +325,13 @@ class SimpleCPU : public BaseCPU
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
-    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
-    Fault hwrei() { return xc->hwrei(); }
+    uint64_t readIpr(int idx, Fault * &fault) { return xc->readIpr(idx, fault); }
+    Fault * setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
+    Fault * hwrei() { return xc->hwrei(); }
     int readIntrFlag() { return xc->readIntrFlag(); }
     void setIntrFlag(int val) { xc->setIntrFlag(val); }
     bool inPalMode() { return xc->inPalMode(); }
-    void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
+    void ev5_trap(Fault * fault) { xc->ev5_trap(fault); }
     bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
 #else
     void syscall() { xc->syscall(); }