Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh

SConscript:
    Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
    Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
    Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
    Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
    Added MIPS as a valid architecture
cpu/exec_context.hh:
    Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
    Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.

--HG--
extra : convert_revision : b1ab34b7569db531cd1c74f273b24222e63f9007

3 files changed, 7 insertions, 4 deletions

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 2bde053b2..846be831a 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -34,6 +34,7 @@
 #include "mem/mem_req.hh"
 #include "sim/host.hh"
 #include "sim/serialize.hh"
+#include "arch/isa_traits.hh"
 #include "sim/byteswap.hh"
 
 // forward declaration: see functional_memory.hh
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 164da4968..1e1a72af0 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -33,6 +33,8 @@
 #define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
 
 #include "cpu/o3/cpu.hh"
+#include "arch/isa_traits.hh"
+#include "sim/byteswap.hh"
 
 template <class Impl>
 class AlphaFullCPU : public FullO3CPU<Impl>
@@ -220,7 +222,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
         Fault error;
         error = this->mem->read(req, data);
-        data = LittleEndianGuest::gtoh(data);
+        data = gtoh(data);
         return error;
     }
 
@@ -277,7 +279,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 #endif
 
-        return this->mem->write(req, (T)LittleEndianGuest::htog(data));
+        return this->mem->write(req, (T)::htog(data));
     }
 
     template <class T>
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index 1a8411cc1..cd1ed1351 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -29,7 +29,7 @@
 // Remove this later; used only for debugging.
 #define OPCODE(X)                       (X >> 26) & 0x3f
 
-
+#include "arch/isa_traits.hh"
 #include "sim/byteswap.hh"
 #include "cpu/exetrace.hh"
 #include "mem/base_mem.hh"
@@ -535,7 +535,7 @@ SimpleFetch<Impl>::fetch()
             assert(offset <= cacheBlkSize - instSize);
 
             // Get the instruction from the array of the cache line.
-            inst = LittleEndianGuest::gtoh(*reinterpret_cast<MachInst *>
+            inst = gtoh(*reinterpret_cast<MachInst *>
                         (&cacheData[offset]));
 
             // Create a new DynInst from the instruction fetched.