diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2004-01-30 16:01:26 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2004-01-30 16:01:26 -0500 |
| commit | 4ae64216c3c27e9f1e35ce93114f932f3d2c3361 (patch) | |
| tree | fe3ca24667628af7c2e5a94a3bcae585fb492855 /cpu | |
| parent | a0c3e61d320e72bbdddf4cea1413f6638e0faf45 (diff) | |
| parent | 2f4f7aacf77dea16795a4052613da6092f6efc31 (diff) | |
| download | gem5-4ae64216c3c27e9f1e35ce93114f932f3d2c3361.tar.xz | |
Merge
--HG--
extra : convert_revision : 8690e31b64235874d74ea4a1123a408610fb115b
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index adbd17a35..0d5fc4077 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -349,7 +349,7 @@ SimpleCPU::read(Addr addr, T& data, unsigned flags) // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && dcacheInterface->doEvents) { + if (result != MA_HIT && dcacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastDcacheStall = curTick; unscheduleTickEvent(); @@ -432,7 +432,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && dcacheInterface->doEvents) { + if (result != MA_HIT && dcacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastDcacheStall = curTick; unscheduleTickEvent(); @@ -635,7 +635,7 @@ SimpleCPU::tick() // Ugly hack to get an event scheduled *only* if the access is // a miss. We really should add first-class support for this // at some point. - if (result != MA_HIT && icacheInterface->doEvents) { + if (result != MA_HIT && icacheInterface->doEvents()) { memReq->completionEvent = &cacheCompletionEvent; lastIcacheStall = curTick; unscheduleTickEvent(); |