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| author | Nathan Binkert <binkertn@umich.edu> | 2004-02-20 15:22:41 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2004-02-20 15:22:41 -0500 |
| commit | 695d51e5137f43052dc54e211eb1ab239100008d (patch) | |
| tree | 21684d6b662765ac351a51845e58b0810dbe34a3 /cpu | |
| parent | 38e8cb8df13496193190fec8dbd8ebc288dca85e (diff) | |
| download | gem5-695d51e5137f43052dc54e211eb1ab239100008d.tar.xz | |
make uncacheable stuff happen again
cpu/simple_cpu/simple_cpu.cc:
Allow requests to be uncacheable
--HG--
extra : convert_revision : 7ab1442f2eec3763d5bc6a6f37b11f663851b12c
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/simple_cpu/simple_cpu.cc | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc index efbe66020..d039890c7 100644 --- a/cpu/simple_cpu/simple_cpu.cc +++ b/cpu/simple_cpu/simple_cpu.cc @@ -343,7 +343,6 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags) memReq->cmd = Read; memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~UNCACHEABLE; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -426,7 +425,6 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) memcpy(memReq->data,(uint8_t *)&data,memReq->size); memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~UNCACHEABLE; MemAccessResult result = dcacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is @@ -629,7 +627,6 @@ SimpleCPU::tick() memReq->completionEvent = NULL; memReq->time = curTick; - memReq->flags &= ~UNCACHEABLE; MemAccessResult result = icacheInterface->access(memReq); // Ugly hack to get an event scheduled *only* if the access is |