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authorKorey Sewell <ksewell@umich.edu>2006-05-02 20:05:16 -0400
committerKorey Sewell <ksewell@umich.edu>2006-05-02 20:05:16 -0400
commit97429d8eeede120a2a78407f3573aa7a05075a89 (patch)
treec0f39da983c4064012a0b44f14f382c98a1e1704 /cpu
parent2d077df1a0bbef0ec6ed4f89132c70d6d870a8d9 (diff)
downloadgem5-97429d8eeede120a2a78407f3573aa7a05075a89.tar.xz
Redo the FloatRegFile using unsigned integers
Edit the convert_and_round function which access FloatRegFile arch/isa_parser.py: recognize when we are writing a 'uint64_t' FloatReg and set the width appropriately arch/mips/isa/decoder.isa: Send a 'float' to the convert function instead of a unsigned word. Do this so we dont have to worry about the bit manipulation ourselves. We can just concern ourselves with values. Use unsigned double to get movd... arch/mips/isa/formats/fp.isa: float debug statement arch/mips/isa_traits.cc: add different versions of convert_and_round functions arch/mips/isa_traits.hh: Use an array of uint32_t unsigned integers to represent the Floating Point Regfile configs/test/hello_mips: basic FP program cpu/simple/cpu.hh: spacing --HG-- extra : convert_revision : a6fca91ad6365c83025f1131d71fa1b8ee76d7bc
Diffstat (limited to 'cpu')
-rw-r--r--cpu/simple/cpu.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 3640348a3..af585a2e5 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -369,7 +369,7 @@ class SimpleCPU : public BaseCPU
}
void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
cpuXC->setFloatRegBits(reg_idx, val, width);