Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.

arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45

43 files changed, 360 insertions, 335 deletions

diff --git a/cpu/base.cc b/cpu/base.cc
index 8b94b8533..5a7ecf152 100644
--- a/cpu/base.cc
+++ b/cpu/base.cc
@@ -250,7 +250,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
     }
 
 #if FULL_SYSTEM
-    for (int i = 0; i < NumInterruptLevels; ++i)
+    for (int i = 0; i < TheISA::NumInterruptLevels; ++i)
         interrupts[i] = oldCPU->interrupts[i];
     intstatus = oldCPU->intstatus;
 
@@ -285,7 +285,7 @@ BaseCPU::post_interrupt(int int_num, int index)
 {
     DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
 
-    if (int_num < 0 || int_num >= NumInterruptLevels)
+    if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
         panic("int_num out of bounds\n");
 
     if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -301,7 +301,7 @@ BaseCPU::clear_interrupt(int int_num, int index)
 {
     DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
 
-    if (int_num < 0 || int_num >= NumInterruptLevels)
+    if (int_num < 0 || int_num >= TheISA::NumInterruptLevels)
         panic("int_num out of bounds\n");
 
     if (index < 0 || index >= sizeof(uint64_t) * 8)
@@ -325,14 +325,14 @@ BaseCPU::clear_interrupts()
 void
 BaseCPU::serialize(std::ostream &os)
 {
-    SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+    SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
     SERIALIZE_SCALAR(intstatus);
 }
 
 void
 BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
 {
-    UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
+    UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels);
     UNSERIALIZE_SCALAR(intstatus);
 }
 
diff --git a/cpu/base.hh b/cpu/base.hh
index 2bd1210d8..ab52e7b81 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -48,6 +48,7 @@ class ExecContext;
 class BaseCPU : public SimObject
 {
   protected:
+    typedef TheISA::Addr Addr;
     // CPU's clock period in terms of the number of ticks of curTime.
     Tick clock;
 
@@ -58,7 +59,7 @@ class BaseCPU : public SimObject
 
 #if FULL_SYSTEM
   protected:
-    uint64_t interrupts[NumInterruptLevels];
+    uint64_t interrupts[TheISA::NumInterruptLevels];
     uint64_t intstatus;
 
   public:
@@ -68,7 +69,7 @@ class BaseCPU : public SimObject
     bool checkInterrupts;
 
     bool check_interrupt(int int_num) const {
-        if (int_num > NumInterruptLevels)
+        if (int_num > TheISA::NumInterruptLevels)
             panic("int_num out of bounds\n");
 
         return interrupts[int_num] != 0;
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 59a12f2d0..9901c90af 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -79,7 +79,7 @@ BaseDynInst<Impl>::BaseDynInst(MachInst machInst, Addr inst_PC,
 }
 
 template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(StaticInstPtr<ISA> &_staticInst)
+BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
     : staticInst(_staticInst), traceData(NULL)
 {
     initVars();
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 2c91db99c..dd429fc91 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -51,7 +51,6 @@
  */
 
 // Forward declaration.
-template <class ISA>
 class StaticInstPtr;
 
 template <class Impl>
@@ -61,25 +60,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
     // Typedef for the CPU.
     typedef typename Impl::FullCPU FullCPU;
 
-    //Typedef to get the ISA.
-    typedef typename Impl::ISA ISA;
-
     /// Binary machine instruction type.
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /// Memory address type.
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr Addr;
     /// Logical register index type.
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
     /// Integer register index type.
-    typedef typename ISA::IntReg   IntReg;
+    typedef TheISA::IntReg IntReg;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
     };
 
     /** The static inst used by this dyn inst. */
-    StaticInstPtr<ISA> staticInst;
+    StaticInstPtr staticInst;
 
     ////////////////////////////////////////////
     //
@@ -214,7 +210,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
                 FullCPU *cpu);
 
     /** BaseDynInst constructor given a static inst pointer. */
-    BaseDynInst(StaticInstPtr<ISA> &_staticInst);
+    BaseDynInst(StaticInstPtr &_staticInst);
 
     /** BaseDynInst destructor. */
     ~BaseDynInst();
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 7e195af23..7e905e7d3 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -35,6 +35,7 @@
 #include "sim/host.hh"
 #include "sim/serialize.hh"
 #include "arch/isa_traits.hh"
+//#include "arch/isa_registers.hh"
 #include "sim/byteswap.hh"
 
 // forward declaration: see functional_memory.hh
@@ -66,6 +67,11 @@ namespace Kernel { class Binning; class Statistics; }
 
 class ExecContext
 {
+  protected:
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::Addr Addr;
+    typedef TheISA::MachInst MachInst;
+    typedef TheISA::MiscRegFile MiscRegFile;
   public:
     enum Status
     {
@@ -431,15 +437,15 @@ class ExecContext
     void trap(Fault * fault);
 
 #if !FULL_SYSTEM
-    IntReg getSyscallArg(int i)
+    TheISA::IntReg getSyscallArg(int i)
     {
-        return regs.intRegFile[ArgumentReg0 + i];
+        return regs.intRegFile[TheISA::ArgumentReg0 + i];
     }
 
     // used to shift args for indirect syscall
-    void setSyscallArg(int i, IntReg val)
+    void setSyscallArg(int i, TheISA::IntReg val)
     {
-        regs.intRegFile[ArgumentReg0 + i] = val;
+        regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
     }
 
     void setSyscallReturn(SyscallReturn return_value)
@@ -451,11 +457,11 @@ class ExecContext
         if (return_value.successful()) {
             // no error
             regs.intRegFile[RegA3] = 0;
-            regs.intRegFile[ReturnValueReg] = return_value.value();
+            regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
         } else {
             // got an error, return details
-            regs.intRegFile[RegA3] = (IntReg) -1;
-            regs.intRegFile[ReturnValueReg] = -return_value.value();
+            regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
+            regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
         }
     }
 
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 48d8966d8..d37c48ddd 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -46,13 +46,15 @@ namespace Trace {
 class InstRecord : public Record
 {
   protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::IntRegFile IntRegFile;
 
     // The following fields are initialized by the constructor and
     // thus guaranteed to be valid.
     BaseCPU *cpu;
     // need to make this ref-counted so it doesn't go away before we
     // dump the record
-    StaticInstPtr<TheISA> staticInst;
+    StaticInstPtr staticInst;
     Addr PC;
     bool misspeculating;
     unsigned thread;
@@ -92,7 +94,7 @@ class InstRecord : public Record
 
   public:
     InstRecord(Tick _cycle, BaseCPU *_cpu,
-               const StaticInstPtr<TheISA> &_staticInst,
+               const StaticInstPtr &_staticInst,
                Addr _pc, bool spec, int _thread)
         : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
           misspeculating(spec), thread(_thread)
@@ -169,8 +171,8 @@ InstRecord::setRegs(const IntRegFile &regs)
 inline
 InstRecord *
 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
-              const StaticInstPtr<TheISA> staticInst,
-              Addr pc, int thread = 0)
+              const StaticInstPtr staticInst,
+              TheISA::Addr pc, int thread = 0)
 {
     if (DTRACE(InstExec) &&
         (InstRecord::traceMisspec() || !xc->misspeculating())) {
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 27f790fac..5a4024587 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -44,6 +44,7 @@
 #include "sim/stats.hh"
 
 using namespace std;
+using namespace TheISA;
 
 int TESTER_ALLOCATOR=0;
 
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 7abcf017a..76a89ff2c 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -42,6 +42,8 @@
 class ExecContext;
 class MemTest : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
 
     MemTest(const std::string &name,
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh
index a97ce455c..78efe1e43 100644
--- a/cpu/o3/2bit_local_pred.hh
+++ b/cpu/o3/2bit_local_pred.hh
@@ -30,11 +30,13 @@
 #define __CPU_O3_CPU_2BIT_LOCAL_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class DefaultBP
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 606f9fa0a..bf3556b8e 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -39,8 +39,10 @@
 template <class Impl>
 class AlphaFullCPU : public FullO3CPU<Impl>
 {
+  protected:
+    typedef AlphaISA::Addr Addr;
+    typedef TheISA::IntReg IntReg;
   public:
-    typedef typename Impl::ISA AlphaISA;
     typedef typename Impl::Params Params;
 
   public:
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 408676331..6736cf9bc 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -282,7 +282,7 @@ AlphaFullCPU<Impl>::hwrei()
     if (!inPalMode())
         return UnimplementedOpcodeFault;
 
-    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+    this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
 //    kernelStats.hwrei();
 
@@ -337,7 +337,7 @@ AlphaFullCPU<Impl>::trap(Fault * fault)
     if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
-    typename AlphaISA::InternalProcReg *ipr = getIpr();
+    AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
     if (fault != InterruptFault || !inPalMode(PC))
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 77dcbaf74..22be2aae5 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -48,21 +48,18 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** Typedef for the CPU. */
     typedef typename Impl::FullCPU FullCPU;
 
-    /** Typedef to get the ISA. */
-    typedef typename Impl::ISA ISA;
-
     /** Binary machine instruction type. */
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /** Memory address type. */
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr	   Addr;
     /** Logical register index type. */
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
     /** Integer register index type. */
-    typedef typename ISA::IntReg   IntReg;
+    typedef TheISA::IntReg   IntReg;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
   public:
@@ -71,7 +68,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
                  FullCPU *cpu);
 
     /** BaseDynInst constructor given a static inst pointer. */
-    AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst);
+    AlphaDynInst(StaticInstPtr &_staticInst);
 
     /** Executes the instruction.*/
     Fault * execute()
@@ -130,22 +127,22 @@ class AlphaDynInst : public BaseDynInst<Impl>
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst<ISA> *si, int idx)
+    uint64_t readIntReg(const StaticInst *si, int idx)
     {
         return this->cpu->readIntReg(_srcRegIdx[idx]);
     }
 
-    float readFloatRegSingle(const StaticInst<ISA> *si, int idx)
+    float readFloatRegSingle(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegSingle(_srcRegIdx[idx]);
     }
 
-    double readFloatRegDouble(const StaticInst<ISA> *si, int idx)
+    double readFloatRegDouble(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegDouble(_srcRegIdx[idx]);
     }
 
-    uint64_t readFloatRegInt(const StaticInst<ISA> *si, int idx)
+    uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         return this->cpu->readFloatRegInt(_srcRegIdx[idx]);
     }
@@ -153,25 +150,25 @@ class AlphaDynInst : public BaseDynInst<Impl>
     /** @todo: Make results into arrays so they can handle multiple dest
      *  registers.
      */
-    void setIntReg(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setIntReg(_destRegIdx[idx], val);
         this->instResult.integer = val;
     }
 
-    void setFloatRegSingle(const StaticInst<ISA> *si, int idx, float val)
+    void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         this->cpu->setFloatRegSingle(_destRegIdx[idx], val);
         this->instResult.fp = val;
     }
 
-    void setFloatRegDouble(const StaticInst<ISA> *si, int idx, double val)
+    void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         this->cpu->setFloatRegDouble(_destRegIdx[idx], val);
         this->instResult.dbl = val;
     }
 
-    void setFloatRegInt(const StaticInst<ISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         this->cpu->setFloatRegInt(_destRegIdx[idx], val);
         this->instResult.integer = val;
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index b20af48cd..9f9df3da1 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -50,7 +50,7 @@ AlphaDynInst<Impl>::AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC,
 }
 
 template <class Impl>
-AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr<AlphaISA> &_staticInst)
+AlphaDynInst<Impl>::AlphaDynInst(StaticInstPtr &_staticInst)
     : BaseDynInst<Impl>(_staticInst)
 {
     // Make sure to have the renamed register entries set to the same
diff --git a/cpu/o3/alpha_impl.hh b/cpu/o3/alpha_impl.hh
index 6c1156041..5e39fcb37 100644
--- a/cpu/o3/alpha_impl.hh
+++ b/cpu/o3/alpha_impl.hh
@@ -51,11 +51,8 @@ class AlphaFullCPU;
  */
 struct AlphaSimpleImpl
 {
-    /** The ISA to be used. */
-    typedef AlphaISA ISA;
-
     /** The type of MachInst. */
-    typedef ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
 
     /** The CPU policy to be used (ie fetch, decode, etc.). */
     typedef SimpleCPUPolicy<AlphaSimpleImpl> CPUPol;
diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh
index 0a77b83dc..c874f9e04 100644
--- a/cpu/o3/bpred_unit.hh
+++ b/cpu/o3/bpred_unit.hh
@@ -53,6 +53,8 @@
 template<class Impl>
 class TwobitBPredUnit
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
diff --git a/cpu/o3/bpred_unit_impl.hh b/cpu/o3/bpred_unit_impl.hh
index 9cb2e0490..8d16a0cdf 100644
--- a/cpu/o3/bpred_unit_impl.hh
+++ b/cpu/o3/bpred_unit_impl.hh
@@ -98,6 +98,8 @@ TwobitBPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC)
     // Save off record of branch stuff so the RAS can be fixed
     // up once it's done.
 
+    using TheISA::MachInst;
+
     bool pred_taken = false;
     Addr target;
 
diff --git a/cpu/o3/btb.cc b/cpu/o3/btb.cc
index 7671e61e2..2d39c3856 100644
--- a/cpu/o3/btb.cc
+++ b/cpu/o3/btb.cc
@@ -30,6 +30,8 @@
 #include "base/trace.hh"
 #include "cpu/o3/btb.hh"
 
+using namespace TheISA;
+
 DefaultBTB::DefaultBTB(unsigned _numEntries,
                        unsigned _tagBits,
                        unsigned _instShiftAmt)
diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh
index a4ddfecb4..f443ddbaf 100644
--- a/cpu/o3/btb.hh
+++ b/cpu/o3/btb.hh
@@ -30,10 +30,12 @@
 #define __CPU_O3_CPU_BTB_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class DefaultBTB
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     struct BTBEntry
     {
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 6ddc8d6b9..580c1a316 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -52,7 +52,6 @@ class SimpleCommit
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index adc7b6bbc..ffa157fbb 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -84,14 +84,14 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       regFile(params.numPhysIntRegs, params.numPhysFloatRegs),
 
-      freeList(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-               Impl::ISA::NumFloatRegs, params.numPhysFloatRegs),
+      freeList(TheISA::NumIntRegs, params.numPhysIntRegs,
+               TheISA::NumFloatRegs, params.numPhysFloatRegs),
 
-      renameMap(Impl::ISA::NumIntRegs, params.numPhysIntRegs,
-                Impl::ISA::NumFloatRegs, params.numPhysFloatRegs,
-                Impl::ISA::NumMiscRegs,
-                Impl::ISA::ZeroReg,
-                Impl::ISA::ZeroReg + Impl::ISA::NumIntRegs),
+      renameMap(TheISA::NumIntRegs, params.numPhysIntRegs,
+                TheISA::NumFloatRegs, params.numPhysFloatRegs,
+                TheISA::NumMiscRegs,
+                TheISA::ZeroReg,
+                TheISA::ZeroReg + TheISA::NumIntRegs),
 
       rob(params.numROBEntries, params.squashWidth),
 
@@ -254,13 +254,13 @@ FullO3CPU<Impl>::init()
         ExecContext *src_xc = thread[0];
 #endif
         // First loop through the integer registers.
-        for (int i = 0; i < Impl::ISA::NumIntRegs; ++i)
+        for (int i = 0; i < TheISA::NumIntRegs; ++i)
         {
             regFile.intRegFile[i] = src_xc->regs.intRegFile[i];
         }
 
         // Then loop through the floating point registers.
-        for (int i = 0; i < Impl::ISA::NumFloatRegs; ++i)
+        for (int i = 0; i < TheISA::NumFloatRegs; ++i)
         {
             regFile.floatRegFile[i].d = src_xc->regs.floatRegFile.d[i];
             regFile.floatRegFile[i].q = src_xc->regs.floatRegFile.q[i];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..321d61dce 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU
 {
   public:
     //Put typedefs from the Impl here.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPolicy;
     typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+    { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+    { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh
index 42313d83a..bae9a7015 100644
--- a/cpu/o3/decode.hh
+++ b/cpu/o3/decode.hh
@@ -39,7 +39,6 @@ class SimpleDecode
 {
   private:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::Params Params;
@@ -51,7 +50,7 @@ class SimpleDecode
     typedef typename CPUPol::TimeStruct TimeStruct;
 
     // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
+    typedef TheISA::Addr Addr;
 
   public:
     // The only time decode will become blocked is if dispatch becomes
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 5443d274e..e4d374c1d 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -49,7 +49,6 @@ class SimpleFetch
 {
   public:
     /** Typedefs from Impl. */
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
@@ -61,7 +60,8 @@ class SimpleFetch
     typedef typename CPUPol::TimeStruct TimeStruct;
 
     /** Typedefs from ISA. */
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
+    typedef TheISA::Addr Addr;
 
   public:
     enum Status {
@@ -141,7 +141,7 @@ class SimpleFetch
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = ISA::realPCToFetchPC(addr);
+        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
diff --git a/cpu/o3/free_list.hh b/cpu/o3/free_list.hh
index 733d142fc..0b85dba1e 100644
--- a/cpu/o3/free_list.hh
+++ b/cpu/o3/free_list.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 #include <queue>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "base/trace.hh"
 #include "base/traceflags.hh"
 #include "cpu/o3/comm.hh"
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index af23c6f45..1e370d4e6 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -45,7 +45,6 @@ class SimpleIEW
 {
   private:
     //Typedefs from Impl
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index b8a2b4dc9..85217dd10 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -256,7 +256,7 @@ SimpleIEW<Impl>::squashDueToBranch(DynInstPtr &inst)
     toCommit->branchMispredict = true;
     // Prediction was incorrect, so send back inverse.
     toCommit->branchTaken = inst->readNextPC() !=
-        (inst->readPC() + sizeof(MachInst));
+        (inst->readPC() + sizeof(TheISA::MachInst));
 }
 
 template<class Impl>
diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh
index bbc4162a6..fd7f5fe1c 100644
--- a/cpu/o3/ras.hh
+++ b/cpu/o3/ras.hh
@@ -30,10 +30,12 @@
 #define __CPU_O3_CPU_RAS_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 
 class ReturnAddrStack
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     ReturnAddrStack(unsigned numEntries);
 
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 5aafd5495..655a3cad9 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -52,6 +52,11 @@ using namespace EV5;
 template <class Impl>
 class PhysRegFile
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::MiscRegFile MiscRegFile;
     //Note that most of the definitions of the IntReg, FloatReg, etc. exist
     //within the Impl/ISA class and not within this PhysRegFile class.
 
@@ -62,7 +67,6 @@ class PhysRegFile
     //Will make these registers public for now, but they probably should
     //be private eventually with some accessor functions.
   public:
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
 
     PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -281,73 +285,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
     uint64_t retval = 0;    // return value, default 0
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PALtemp23:
-      case ISA::IPR_PAL_BASE:
-
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
-      case ISA::IPR_ISR:
-      case ISA::IPR_EXC_ADDR:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_MCSR:
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
-      case ISA::IPR_SIRR:
-      case ISA::IPR_ICSR:
-      case ISA::IPR_ICM:
-      case ISA::IPR_DTB_CM:
-      case ISA::IPR_IPLR:
-      case ISA::IPR_INTID:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PALtemp23:
+      case TheISA::IPR_PAL_BASE:
+
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
+      case TheISA::IPR_ISR:
+      case TheISA::IPR_EXC_ADDR:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_MCSR:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
+      case TheISA::IPR_SIRR:
+      case TheISA::IPR_ICSR:
+      case TheISA::IPR_ICM:
+      case TheISA::IPR_DTB_CM:
+      case TheISA::IPR_IPLR:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_PMCTR:
         // no side-effect
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
         retval |= curTick  & ULL(0x00000000ffffffff);
         break;
 
-      case ISA::IPR_VA:
+      case TheISA::IPR_VA:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_VA_FORM:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_IFAULT_VA_FORM:
-      case ISA::IPR_EXC_MASK:
-      case ISA::IPR_EXC_SUM:
+      case TheISA::IPR_VA_FORM:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_IFAULT_VA_FORM:
+      case TheISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         {
-            typename ISA::PTE &pte = cpu->dtb->index(1);
+            TheISA::PTE &pte = cpu->dtb->index(1);
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -360,15 +364,15 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
         break;
 
         // write only registers
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
-      case ISA::IPR_ALT_MODE:
-      case ISA::IPR_DTB_IA:
-      case ISA::IPR_DTB_IAP:
-      case ISA::IPR_ITB_IA:
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
+      case TheISA::IPR_ALT_MODE:
+      case TheISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IAP:
+      case TheISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IAP:
         fault = UnimplementedOpcodeFault;
         break;
 
@@ -390,195 +394,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     uint64_t old;
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PAL_BASE:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PAL_BASE:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_PMCTR:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_CC_CTL:
+      case TheISA::IPR_CC_CTL:
         // This IPR resets the cycle counter.  We assume this only
         // happens once... let's verify that.
         assert(ipr[idx] == 0);
         ipr[idx] = 1;
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         // This IPR only writes the upper 64 bits.  It's ok to write
         // all 64 here since we mask out the lower 32 in rpcc (see
         // isa_desc).
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_PALtemp23:
+      case TheISA::IPR_PALtemp23:
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         // write entire quad w/ no side-effect, tag is forthcoming
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_EXC_ADDR:
+      case TheISA::IPR_EXC_ADDR:
         // second least significant bit in PC is always zero
         ipr[idx] = val & ~2;
         break;
 
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
         // only write least significant four bits - privilege mask
         ipr[idx] = val & 0xf;
         break;
 
-      case ISA::IPR_IPLR:
+      case TheISA::IPR_IPLR:
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         break;
 
-      case ISA::IPR_DTB_CM:
+      case TheISA::IPR_DTB_CM:
 
-      case ISA::IPR_ICM:
+      case TheISA::IPR_ICM:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_ALT_MODE:
+      case TheISA::IPR_ALT_MODE:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_MCSR:
+      case TheISA::IPR_MCSR:
         // more here after optimization...
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_SIRR:
+      case TheISA::IPR_SIRR:
         // only write software interrupt mask
         ipr[idx] = val & 0x7fff0;
         break;
 
-      case ISA::IPR_ICSR:
+      case TheISA::IPR_ICSR:
         ipr[idx] = val & ULL(0xffffff0300);
         break;
 
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_MVPTBR:
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_MVPTBR:
         ipr[idx] = val & ULL(0xffffffffc0000000);
         break;
 
-      case ISA::IPR_DC_TEST_CTL:
+      case TheISA::IPR_DC_TEST_CTL:
         ipr[idx] = val & 0x1ffb;
         break;
 
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
         ipr[idx] = val & 0x3f;
         break;
 
-      case ISA::IPR_ITB_ASN:
+      case TheISA::IPR_ITB_ASN:
         ipr[idx] = val & 0x7f0;
         break;
 
-      case ISA::IPR_DTB_ASN:
+      case TheISA::IPR_DTB_ASN:
         ipr[idx] = val & ULL(0xfe00000000000000);
         break;
 
-      case ISA::IPR_EXC_SUM:
-      case ISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
+      case TheISA::IPR_EXC_MASK:
         // any write to this register clears it
         ipr[idx] = 0;
         break;
 
-      case ISA::IPR_INTID:
-      case ISA::IPR_SL_RCV:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_ITB_PTE_TEMP:
-      case ISA::IPR_DTB_PTE_TEMP:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_SL_RCV:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_ITB_PTE_TEMP:
+      case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
         return UnimplementedOpcodeFault;
 
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
         // the following are write only
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushAll();
         break;
 
-      case ISA::IPR_DTB_IAP:
+      case TheISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushProcesses();
         break;
 
-      case ISA::IPR_DTB_IS:
+      case TheISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
+        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
         break;
 
-      case ISA::IPR_DTB_TAG: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_DTB_TAG: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
-          if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
+          if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
               panic("PTE GH field != 0");
 
           // write entire quad
           ipr[idx] = val;
 
           // construct PTE for new entry
-          pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
-          pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
-          pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
-          pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
-          pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
+          pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
           cpu->dtb->insert(val, pte);
       }
         break;
 
-      case ISA::IPR_ITB_PTE: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_ITB_PTE: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
           if (ITB_PTE_GH(val) != 0)
@@ -594,32 +598,32 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
           pte.fonr = ITB_PTE_FONR(val);
           pte.fonw = ITB_PTE_FONW(val);
           pte.asma = ITB_PTE_ASMA(val);
-          pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
+          pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
+          cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
       }
         break;
 
-      case ISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushAll();
         break;
 
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushProcesses();
         break;
 
-      case ISA::IPR_ITB_IS:
+      case TheISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
+        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
         break;
 
       default:
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..9781480b6 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
 {
   public:
     // Typedefs from the Impl.
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::CPUPol CPUPol;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,8 @@ class SimpleRename
     typedef typename CPUPol::RenameMap RenameMap;
 
     // Typedefs from the ISA.
-    typedef typename ISA::Addr Addr;
+    typedef TheISA::Addr Addr;
+    typedef TheISA::RegIndex RegIndex;
 
   public:
     // Rename will block if ROB becomes full or issue queue becomes full,
diff --git a/cpu/o3/rename_map.hh b/cpu/o3/rename_map.hh
index c44c7a1ea..57be4a64a 100644
--- a/cpu/o3/rename_map.hh
+++ b/cpu/o3/rename_map.hh
@@ -38,9 +38,13 @@
 #include <vector>
 
 #include "cpu/o3/free_list.hh"
+//For RegIndex
+#include "arch/isa_traits.hh"
 
 class SimpleRenameMap
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     /**
      * Pair of a logical register and a physical register.  Tells the
diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh
index 29ec48007..1185564ad 100644
--- a/cpu/o3/rob.hh
+++ b/cpu/o3/rob.hh
@@ -47,6 +47,8 @@
 template <class Impl>
 class ROB
 {
+  protected:
+    typedef TheISA::RegIndex RegIndex;
   public:
     //Typedefs from the Impl.
     typedef typename Impl::FullCPU FullCPU;
diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh
index bcd590384..c67d30fcb 100644
--- a/cpu/o3/store_set.hh
+++ b/cpu/o3/store_set.hh
@@ -31,11 +31,13 @@
 
 #include <vector>
 
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/inst_seq.hh"
 
 class StoreSet
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     typedef unsigned SSID;
 
diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh
index 58ea1a7d9..6cfd24cfb 100644
--- a/cpu/o3/tournament_pred.hh
+++ b/cpu/o3/tournament_pred.hh
@@ -30,11 +30,13 @@
 #define __CPU_O3_CPU_TOURNAMENT_PRED_HH__
 
 // For Addr type.
-#include "arch/alpha/isa_traits.hh"
+#include "arch/isa_traits.hh"
 #include "cpu/o3/sat_counter.hh"
 
 class TournamentBP
 {
+  protected:
+    typedef TheISA::Addr Addr;
   public:
     /**
      * Default branch predictor constructor.
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 21fe05b6a..7976632d9 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -77,7 +77,6 @@ class OoOCPU : public BaseCPU
   private:
     typedef typename Impl::DynInst DynInst;
     typedef typename Impl::DynInstPtr DynInstPtr;
-    typedef typename Impl::ISA ISA;
 
   public:
     // main simulation loop (one cycle)
@@ -378,12 +377,12 @@ class OoOCPU : public BaseCPU
   private:
     InstSeqNum globalSeqNum;
 
-    DynInstPtr renameTable[ISA::TotalNumRegs];
-    DynInstPtr commitTable[ISA::TotalNumRegs];
+    DynInstPtr renameTable[TheISA::TotalNumRegs];
+    DynInstPtr commitTable[TheISA::TotalNumRegs];
 
     // Might need a table of the shadow registers as well.
 #if FULL_SYSTEM
-    DynInstPtr palShadowTable[ISA::NumIntRegs];
+    DynInstPtr palShadowTable[TheISA::NumIntRegs];
 #endif
 
   public:
@@ -402,47 +401,47 @@ class OoOCPU : public BaseCPU
     // rename table of DynInsts.  Also these likely shouldn't be called very
     // often, other than when adding things into the xc during say a syscall.
 
-    uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
+    uint64_t readIntReg(StaticInst *si, int idx)
     {
         return xc->readIntReg(si->srcRegIdx(idx));
     }
 
-    float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
+    float readFloatRegSingle(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegSingle(reg_idx);
     }
 
-    double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
+    double readFloatRegDouble(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegDouble(reg_idx);
     }
 
-    uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
+    uint64_t readFloatRegInt(StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegInt(reg_idx);
     }
 
-    void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setIntReg(StaticInst *si, int idx, uint64_t val)
     {
         xc->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
+    void setFloatRegSingle(StaticInst *si, int idx, float val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegSingle(reg_idx, val);
     }
 
-    void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
+    void setFloatRegDouble(StaticInst *si, int idx, double val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegDouble(reg_idx, val);
     }
 
-    void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegInt(reg_idx, val);
@@ -479,7 +478,7 @@ class OoOCPU : public BaseCPU
     // We fold in the PISA 64- to 32-bit conversion here as well.
     Addr icacheBlockAlignPC(Addr addr)
     {
-        addr = ISA::realPCToFetchPC(addr);
+        addr = TheISA::realPCToFetchPC(addr);
         return (addr & ~(cacheBlkMask));
     }
 
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index 83fbc3e2d..7a294866d 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
 #if FULL_SYSTEM
 extern "C"
 void
-sched_break_pc_sys(System *sys, Addr addr)
+sched_break_pc_sys(System *sys, TheISA::Addr addr)
 {
     new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
 }
 
 extern "C"
 void
-sched_break_pc(Addr addr)
+sched_break_pc(TheISA::Addr addr)
 {
      for (vector<System *>::iterator sysi = System::systemList.begin();
           sysi != System::systemList.end(); ++sysi) {
diff --git a/cpu/pc_event.hh b/cpu/pc_event.hh
index 7fa3902cc..3033a3cfd 100644
--- a/cpu/pc_event.hh
+++ b/cpu/pc_event.hh
@@ -39,6 +39,7 @@ class PCEventQueue;
 class PCEvent
 {
   protected:
+    typedef TheISA::Addr Addr;
     static const Addr badpc = MemReq::inval_addr;
 
   protected:
@@ -64,6 +65,7 @@ class PCEvent
 class PCEventQueue
 {
   protected:
+    typedef TheISA::Addr Addr;
     typedef PCEvent * record_t;
     class MapCompare {
       public:
@@ -132,6 +134,7 @@ PCEvent::remove()
 class BreakPCEvent : public PCEvent
 {
   protected:
+    typedef TheISA::Addr Addr;
     bool remove;
 
   public:
diff --git a/cpu/profile.hh b/cpu/profile.hh
index 58cd7e79f..b55f87a6a 100644
--- a/cpu/profile.hh
+++ b/cpu/profile.hh
@@ -37,6 +37,8 @@
 
 class ProfileNode
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     friend class FunctionProfile;
 
@@ -57,6 +59,8 @@ class ProfileNode
 class Callback;
 class FunctionProfile
 {
+  public:
+    typedef TheISA::Addr Addr;
   private:
     Callback *reset;
     const SymbolTable *symtab;
@@ -68,7 +72,7 @@ class FunctionProfile
     FunctionProfile(const SymbolTable *symtab);
     ~FunctionProfile();
 
-    ProfileNode *consume(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    ProfileNode *consume(ExecContext *xc, StaticInstPtr inst);
     ProfileNode *consume(const std::vector<Addr> &stack);
     void clear();
     void dump(ExecContext *xc, std::ostream &out) const;
@@ -76,7 +80,7 @@ class FunctionProfile
 };
 
 inline ProfileNode *
-FunctionProfile::consume(ExecContext *xc, StaticInstPtr<TheISA> inst)
+FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst)
 {
     if (!trace.trace(xc, inst))
         return NULL;
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6aff94abd..c3f256de9 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -76,7 +76,7 @@
 
 using namespace std;
 //The SimpleCPU does alpha only
-using namespace LittleEndianGuest;
+using namespace AlphaISA;
 
 
 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
@@ -125,7 +125,7 @@ SimpleCPU::SimpleCPU(Params *p)
     xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
     // initialize CPU, including PC
-    TheISA::initCPU(&xc->regs);
+    initCPU(&xc->regs);
 #else
     xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
 #endif // !FULL_SYSTEM
@@ -323,7 +323,7 @@ SimpleCPU::copySrcTranslate(Addr src)
 
     // Make sure block doesn't span page
     if (no_warn &&
-        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
+        (src & PageMask) != ((src + blk_size) & PageMask) &&
         (src >> 40) != 0xfffffc) {
         warn("Copied block source spans pages %x.", src);
         no_warn = false;
@@ -359,7 +359,7 @@ SimpleCPU::copy(Addr dest)
 
     // Make sure block doesn't span page
     if (no_warn &&
-        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
+        (dest & PageMask) != ((dest + blk_size) & PageMask) &&
         (dest >> 40) != 0xfffffc) {
         no_warn = false;
         warn("Copied block destination spans pages %x. ", dest);
@@ -648,20 +648,20 @@ SimpleCPU::tick()
         checkInterrupts = false;
         IntReg *ipr = xc->regs.ipr;
 
-        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
-            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
-                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
-                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
+        if (xc->regs.ipr[IPR_SIRR]) {
+            for (int i = INTLEVEL_SOFTWARE_MIN;
+                 i < INTLEVEL_SOFTWARE_MAX; i++) {
+                if (ipr[IPR_SIRR] & (ULL(1) << i)) {
                     // See table 4-19 of 21164 hardware reference
-                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
+                    ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                     summary |= (ULL(1) << i);
                 }
             }
         }
 
         uint64_t interrupts = xc->cpu->intr_status();
-        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
-            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
+        for (int i = INTLEVEL_EXTERNAL_MIN;
+            i < INTLEVEL_EXTERNAL_MAX; i++) {
             if (interrupts & (ULL(1) << i)) {
                 // See table 4-19 of 21164 hardware reference
                 ipl = i;
@@ -669,16 +669,16 @@ SimpleCPU::tick()
             }
         }
 
-        if (ipr[TheISA::IPR_ASTRR])
+        if (ipr[IPR_ASTRR])
             panic("asynchronous traps not implemented\n");
 
-        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
-            ipr[TheISA::IPR_ISR] = summary;
-            ipr[TheISA::IPR_INTID] = ipl;
+        if (ipl && ipl > xc->regs.ipr[IPR_IPLR]) {
+            ipr[IPR_ISR] = summary;
+            ipr[IPR_INTID] = ipl;
             xc->ev5_trap(InterruptFault);
 
             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                    ipr[TheISA::IPR_IPLR], ipl, summary);
+                    ipr[IPR_IPLR], ipl, summary);
         }
     }
 #endif
@@ -749,7 +749,7 @@ SimpleCPU::tick()
 
         // decode the instruction
         inst = gtoh(inst);
-        curStaticInst = StaticInst<TheISA>::decode(inst);
+        curStaticInst = StaticInst::decode(inst);
 
         traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
                                          xc->regs.pc);
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index e7a447117..8a3900726 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -63,6 +63,8 @@ namespace Trace {
 
 class SimpleCPU : public BaseCPU
 {
+  protected:
+    typedef TheISA::MachInst MachInst;
   public:
     // main simulation loop (one cycle)
     void tick();
@@ -172,7 +174,7 @@ class SimpleCPU : public BaseCPU
     // the next switchover
     Sampler *sampler;
 
-    StaticInstPtr<TheISA> curStaticInst;
+    StaticInstPtr curStaticInst;
 
     class CacheCompletionEvent : public Event
     {
@@ -269,47 +271,47 @@ class SimpleCPU : public BaseCPU
     // storage (which is pretty hard to imagine they would have reason
     // to do).
 
-    uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
+    uint64_t readIntReg(const StaticInst *si, int idx)
     {
         return xc->readIntReg(si->srcRegIdx(idx));
     }
 
-    float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
+    float readFloatRegSingle(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegSingle(reg_idx);
     }
 
-    double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
+    double readFloatRegDouble(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegDouble(reg_idx);
     }
 
-    uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
+    uint64_t readFloatRegInt(const StaticInst *si, int idx)
     {
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
         return xc->readFloatRegInt(reg_idx);
     }
 
-    void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setIntReg(const StaticInst *si, int idx, uint64_t val)
     {
         xc->setIntReg(si->destRegIdx(idx), val);
     }
 
-    void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
+    void setFloatRegSingle(const StaticInst *si, int idx, float val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegSingle(reg_idx, val);
     }
 
-    void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
+    void setFloatRegDouble(const StaticInst *si, int idx, double val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegDouble(reg_idx, val);
     }
 
-    void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
+    void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
     {
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
         xc->setFloatRegInt(reg_idx, val);
diff --git a/cpu/static_inst.cc b/cpu/static_inst.cc
index 54bd9914e..c307dc6fc 100644
--- a/cpu/static_inst.cc
+++ b/cpu/static_inst.cc
@@ -30,19 +30,13 @@
 #include "cpu/static_inst.hh"
 #include "sim/root.hh"
 
-template <class ISA>
-StaticInstPtr<ISA> StaticInst<ISA>::nullStaticInstPtr;
-
-template <class ISA>
-typename StaticInst<ISA>::DecodeCache StaticInst<ISA>::decodeCache;
+StaticInstPtr StaticInst::nullStaticInstPtr;
 
 // Define the decode cache hash map.
-template StaticInst<AlphaISA>::DecodeCache
-StaticInst<AlphaISA>::decodeCache;
+StaticInst::DecodeCache StaticInst::decodeCache;
 
-template <class ISA>
 void
-StaticInst<ISA>::dumpDecodeCacheStats()
+StaticInst::dumpDecodeCacheStats()
 {
     using namespace std;
 
@@ -62,13 +56,8 @@ StaticInst<ISA>::dumpDecodeCacheStats()
     }
 }
 
-
-template StaticInstPtr<AlphaISA>
-StaticInst<AlphaISA>::nullStaticInstPtr;
-
-template <class ISA>
 bool
-StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
 {
     if (isDirectCtrl()) {
         tgt = branchTarget(pc);
@@ -83,6 +72,3 @@ StaticInst<ISA>::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
     return false;
 }
 
-
-// force instantiation of template function(s) above
-template class StaticInst<AlphaISA>;
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh
index 24997eadc..6be30cd31 100644
--- a/cpu/static_inst.hh
+++ b/cpu/static_inst.hh
@@ -208,7 +208,6 @@ class StaticInstBase : public RefCounted
 
 
 // forward declaration
-template <class ISA>
 class StaticInstPtr;
 
 /**
@@ -218,21 +217,20 @@ class StaticInstPtr;
  * that are generic across all ISAs but that differ in details
  * according to the specific ISA being used.
  */
-template <class ISA>
 class StaticInst : public StaticInstBase
 {
   public:
 
     /// Binary machine instruction type.
-    typedef typename ISA::MachInst MachInst;
+    typedef TheISA::MachInst MachInst;
     /// Memory address type.
-    typedef typename ISA::Addr	   Addr;
+    typedef TheISA::Addr	   Addr;
     /// Logical register index type.
-    typedef typename ISA::RegIndex RegIndex;
+    typedef TheISA::RegIndex RegIndex;
 
     enum {
-        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
-        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
+        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
     };
 
 
@@ -247,7 +245,7 @@ class StaticInst : public StaticInstBase
     /// Pointer to a statically allocated "null" instruction object.
     /// Used to give eaCompInst() and memAccInst() something to return
     /// when called on non-memory instructions.
-    static StaticInstPtr<ISA> nullStaticInstPtr;
+    static StaticInstPtr nullStaticInstPtr;
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -256,7 +254,7 @@ class StaticInst : public StaticInstBase
      * just the EA computation.
      */
     virtual const
-    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
 
     /**
      * Memory references only: returns "fake" instruction representing
@@ -265,7 +263,7 @@ class StaticInst : public StaticInstBase
      * just the memory access (not the EA computation).
      */
     virtual const
-    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
+    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
 
     /// The binary machine instruction.
     const MachInst machInst;
@@ -364,7 +362,7 @@ class StaticInst : public StaticInstBase
     /// Decoded instruction cache type.
     /// For now we're using a generic hash_map; this seems to work
     /// pretty well.
-    typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
+    typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
 
     /// A cache of decoded instruction objects.
     static DecodeCache decodeCache;
@@ -378,63 +376,40 @@ class StaticInst : public StaticInstBase
     /// Decode a machine instruction.
     /// @param mach_inst The binary instruction to decode.
     /// @retval A pointer to the corresponding StaticInst object.
-    static
-    StaticInstPtr<ISA> decode(MachInst mach_inst)
-    {
-#ifdef DECODE_CACHE_HASH_STATS
-        // Simple stats on decode hash_map.  Turns out the default
-        // hash function is as good as anything I could come up with.
-        const int dump_every_n = 10000000;
-        static int decodes_til_dump = dump_every_n;
-
-        if (--decodes_til_dump == 0) {
-            dumpDecodeCacheStats();
-            decodes_til_dump = dump_every_n;
-        }
-#endif
-
-        typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
-        if (iter != decodeCache.end()) {
-            return iter->second;
-        }
-
-        StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
-        decodeCache[mach_inst] = si;
-        return si;
-    }
+    //This is defined as inline below.
+    static StaticInstPtr decode(MachInst mach_inst);
 };
 
 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 
 /// Reference-counted pointer to a StaticInst object.
-/// This type should be used instead of "StaticInst<ISA> *" so that
+/// This type should be used instead of "StaticInst *" so that
 /// StaticInst objects can be properly reference-counted.
-template <class ISA>
-class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
+class StaticInstPtr : public RefCountingPtr<StaticInst>
 {
   public:
     /// Constructor.
     StaticInstPtr()
-        : RefCountingPtr<StaticInst<ISA> >()
+        : RefCountingPtr<StaticInst>()
     {
     }
 
-    /// Conversion from "StaticInst<ISA> *".
-    StaticInstPtr(StaticInst<ISA> *p)
-        : RefCountingPtr<StaticInst<ISA> >(p)
+    /// Conversion from "StaticInst *".
+    StaticInstPtr(StaticInst *p)
+        : RefCountingPtr<StaticInst>(p)
     {
     }
 
     /// Copy constructor.
     StaticInstPtr(const StaticInstPtr &r)
-        : RefCountingPtr<StaticInst<ISA> >(r)
+        : RefCountingPtr<StaticInst>(r)
     {
     }
 
     /// Construct directly from machine instruction.
-    /// Calls StaticInst<ISA>::decode().
-    StaticInstPtr(typename ISA::MachInst mach_inst)
-        : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
+    /// Calls StaticInst::decode().
+    StaticInstPtr(TheISA::MachInst mach_inst)
+        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
     {
     }
 
@@ -445,4 +420,29 @@ class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
     }
 };
 
+inline StaticInstPtr
+StaticInst::decode(StaticInst::MachInst mach_inst)
+{
+#ifdef DECODE_CACHE_HASH_STATS
+    // Simple stats on decode hash_map.  Turns out the default
+    // hash function is as good as anything I could come up with.
+    const int dump_every_n = 10000000;
+    static int decodes_til_dump = dump_every_n;
+
+    if (--decodes_til_dump == 0) {
+        dumpDecodeCacheStats();
+        decodes_til_dump = dump_every_n;
+    }
+#endif
+
+    DecodeCache::iterator iter = decodeCache.find(mach_inst);
+    if (iter != decodeCache.end()) {
+        return iter->second;
+    }
+
+    StaticInstPtr si = TheISA::decodeInst(mach_inst);
+    decodeCache[mach_inst] = si;
+    return si;
+}
+
 #endif // __CPU_STATIC_INST_HH__
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
index f81691733..704dc09fa 100644
--- a/cpu/trace/opt_cpu.hh
+++ b/cpu/trace/opt_cpu.hh
@@ -49,6 +49,8 @@ class MemTraceReader;
  */
 class OptCPU : public SimObject
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     typedef int RefIndex;
 
diff --git a/cpu/trace/reader/itx_reader.hh b/cpu/trace/reader/itx_reader.hh
index faec73138..e402b2d52 100644
--- a/cpu/trace/reader/itx_reader.hh
+++ b/cpu/trace/reader/itx_reader.hh
@@ -46,6 +46,9 @@
  */
 class ITXReader : public MemTraceReader
 {
+  protected:
+    typedef TheISA::Addr Addr;
+  private:
     /** Trace file. */
     FILE *trace;