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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-01 00:09:08 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-01 00:09:08 -0500 |
| commit | 69e91d761765b84429dc069b8fa1cd3f25925688 (patch) | |
| tree | e2fe131e39c1ba9aeb5882bd231670a3f8e30304 /cpu | |
| parent | 34da58a698e4119876f04d13c337e9974970f49a (diff) | |
| download | gem5-69e91d761765b84429dc069b8fa1cd3f25925688.tar.xz | |
moved ev5_trap fully into the fault class.
--HG--
extra : convert_revision : 182cdec9a4e05f55edff0c6a114844b9ad2ca8db
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index daa61bb1c..a1c659b51 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -302,7 +302,7 @@ template <class Impl> void AlphaFullCPU<Impl>::trap(Fault fault) { - // Keep in mind that a trap may be initiated by fetch if there's a TLB +/* // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss uint64_t PC = this->commit.readCommitPC(); @@ -318,8 +318,9 @@ AlphaFullCPU<Impl>::trap(Fault fault) if (!fault->isA<InterruptFault>() || !inPalMode(PC)) this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC); - if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* || - fault == InterruptFault && !PC_PAL(regs.pc) */) { + if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>()) + // || fault == InterruptFault && !PC_PAL(regs.pc) + { // traps... skip faulting instruction AlphaISA::MiscReg ipr_exc_addr = this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR); @@ -332,7 +333,7 @@ AlphaFullCPU<Impl>::trap(Fault fault) this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) + (dynamic_cast<AlphaFault *>(fault.get()))->vect()); - this->regFile.setNextPC(PC + sizeof(MachInst)); + this->regFile.setNextPC(PC + sizeof(MachInst));*/ } template <class Impl> |