Build options are set via a build_options file in the

build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. Build option flags are now always defined to 0 or 1, so checks must use '#if' rather than '#ifdef'. SConscript: MySQL detection moved to SConstruct. Add config/*.hh files (via ConfigFile builder). arch/alpha/alpha_memory.cc: arch/alpha/ev5.cc: arch/alpha/ev5.hh: arch/alpha/isa_traits.hh: base/fast_alloc.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: cpu/base.cc: cpu/base.hh: cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/alpha_dyn_inst_impl.hh: cpu/o3/alpha_params.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/fetch_impl.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/regfile.hh: cpu/o3/rename_impl.hh: cpu/o3/rob_impl.hh: cpu/ozone/cpu.hh: cpu/pc_event.cc: cpu/simple/cpu.cc: cpu/simple/cpu.hh: sim/process.cc: sim/process.hh: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. arch/alpha/isa_desc: Convert compile flags from def/undef to 0/1. Set via #include config/*.hh instead of command line. Revamp fenv.h support... most of the ugliness is hidden in base/fenv.hh now. base/mysql.hh: Fix typo in #ifndef guard. build/SConstruct: Build options are set via a build_options file in the build directory instead of being inferred from the name of the build directory. Options are passed to C++ via config/*.hh files instead of via the command line. python/SConscript: Generate m5_build_env directly from scons options instead of indirectly via CPPDEFINES. python/m5/convert.py: Allow '0' and '1' for booleans. Rewrite toBool to use dict. base/fenv.hh: Revamp <fenv.h> support to make it a compile option (so we can test w/o it even if it's present) and to make isa_desc cleaner. --HG-- extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
author: Steve Reinhardt <stever@eecs.umich.edu> 2005-08-30 13:18:54 -0400
committer: Steve Reinhardt <stever@eecs.umich.edu> 2005-08-30 13:18:54 -0400
commit: c4793184bd32e97e8932a9a0355d8a7b8a214752 (patch)
tree: d616bdd39c608898bd5fea6928166175e96d8d79 /cpu
parent: e007aa59e3da2609de92cc6d2cfcd7acf9d4276f (diff)
download: gem5-c4793184bd32e97e8932a9a0355d8a7b8a214752.tar.xz
25 files changed, 113 insertions, 100 deletions
diff --git a/cpu/base.cc b/cpu/base.cc
index 50c777b0d..8d97bc330 100644
--- a/cpu/base.cc
+++ b/cpu/base.cc
@@ -51,7 +51,7 @@ vector<BaseCPU *> BaseCPU::cpuList;
 // been initialized
 int maxThreadsPerCPU = 1;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
     : SimObject(p->name), clock(p->clock), checkInterrupts(true),
       params(p), number_of_threads(p->numberOfThreads), system(p->system)
@@ -122,7 +122,7 @@ BaseCPU::BaseCPU(Params *p)
                 p->max_loads_all_threads, *counter);
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     memset(interrupts, 0, sizeof(interrupts));
     intstatus = 0;
 #endif
@@ -189,7 +189,7 @@ BaseCPU::registerExecContexts()
 {
     for (int i = 0; i < execContexts.size(); ++i) {
         ExecContext *xc = execContexts[i];
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         int id = params->cpu_id;
         if (id != -1)
             id += i;
@@ -219,7 +219,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 
         newXC->takeOverFrom(oldXC);
         assert(newXC->cpu_id == oldXC->cpu_id);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         system->replaceExecContext(newXC, newXC->cpu_id);
 #else
         assert(newXC->process == oldXC->process);
@@ -227,7 +227,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 #endif
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     for (int i = 0; i < NumInterruptLevels; ++i)
         interrupts[i] = oldCPU->interrupts[i];
     intstatus = oldCPU->intstatus;
@@ -235,7 +235,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
 }
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 BaseCPU::post_interrupt(int int_num, int index)
 {
diff --git a/cpu/base.hh b/cpu/base.hh
index e28f15884..b9617a730 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -32,12 +32,13 @@
 #include <vector>
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/sampler/sampler.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_object.hh"
 #include "targetarch/isa_traits.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class System;
 #endif
 
@@ -55,7 +56,7 @@ class BaseCPU : public SimObject
     inline Tick cycles(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   protected:
     uint64_t interrupts[NumInterruptLevels];
     uint64_t intstatus;
@@ -109,7 +110,7 @@ class BaseCPU : public SimObject
         Tick clock;
         bool functionTrace;
         Tick functionTraceStart;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         System *system;
         int cpu_id;
 #endif
@@ -153,7 +154,7 @@ class BaseCPU : public SimObject
      */
     EventQueue **comLoadEventQueue;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     /**
diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc
index 80eb34fd5..d921bd148 100644
--- a/cpu/base_dyn_inst.cc
+++ b/cpu/base_dyn_inst.cc
@@ -166,7 +166,7 @@ BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh
index 3f5f327a6..d29257a52 100644
--- a/cpu/base_dyn_inst.hh
+++ b/cpu/base_dyn_inst.hh
@@ -34,6 +34,7 @@
 
 #include "base/fast_alloc.hh"
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/comm.hh"
@@ -467,7 +468,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
@@ -515,7 +516,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
      * Replace the disjoint functional memory with a unified one and remove
      * this hack.
      */
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     req->paddr = req->vaddr;
 #endif
 
diff --git a/cpu/exec_context.cc b/cpu/exec_context.cc
index 52d5c8d1e..91578bdf1 100644
--- a/cpu/exec_context.cc
+++ b/cpu/exec_context.cc
@@ -31,7 +31,7 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/cprintf.hh"
 #include "kern/kernel_stats.hh"
 #include "sim/serialize.hh"
@@ -43,7 +43,7 @@
 using namespace std;
 
 // constructor
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
                          AlphaITB *_itb, AlphaDTB *_dtb,
                          FunctionalMemory *_mem)
@@ -78,7 +78,7 @@ ExecContext::ExecContext(BaseCPU *_cpu, int _thread_num,
 
 ExecContext::~ExecContext()
 {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     delete kernelStats;
 #endif
 }
@@ -89,7 +89,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext)
 {
     // some things should already be set up
     assert(mem == oldContext->mem);
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     assert(system == oldContext->system);
 #else
     assert(process == oldContext->process);
@@ -106,7 +106,7 @@ ExecContext::takeOverFrom(ExecContext *oldContext)
     oldContext->_status = ExecContext::Unallocated;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 ExecContext::execute(const StaticInstBase *inst)
 {
@@ -124,7 +124,7 @@ ExecContext::serialize(ostream &os)
     SERIALIZE_SCALAR(func_exe_inst);
     SERIALIZE_SCALAR(inst);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->serialize(os);
 #endif
 }
@@ -139,7 +139,7 @@ ExecContext::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(func_exe_inst);
     UNSERIALIZE_SCALAR(inst);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->unserialize(cp, section);
 #endif
 }
@@ -161,7 +161,7 @@ ExecContext::suspend()
     if (status() == Suspended)
         return;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Don't change the status from active if there are pending interrupts
     if (cpu->check_interrupts()) {
         assert(status() == Active);
@@ -197,7 +197,7 @@ ExecContext::halt()
 void
 ExecContext::regStats(const string &name)
 {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     kernelStats->regStats(name + ".kern");
 #endif
 }
@@ -208,7 +208,7 @@ ExecContext::trap(Fault fault)
     //TheISA::trap(fault);    //One possible way to do it...
 
     /** @todo: Going to hack it for now.  Do a true fixup later. */
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ev5_trap(fault);
 #else
     fatal("fault (%d) detected @ PC 0x%08p", fault, readPC());
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 5e105c44d..6a17951f9 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -29,6 +29,7 @@
 #ifndef __CPU_EXEC_CONTEXT_HH__
 #define __CPU_EXEC_CONTEXT_HH__
 
+#include "config/full_system.hh"
 #include "mem/functional/functional.hh"
 #include "mem/mem_req.hh"
 #include "sim/host.hh"
@@ -40,7 +41,7 @@ class FunctionalMemory;
 class PhysicalMemory;
 class BaseCPU;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 #include "sim/system.hh"
 #include "targetarch/alpha_memory.hh"
@@ -121,7 +122,7 @@ class ExecContext
     // it belongs.  For full-system mode, this is the system CPU ID.
     int cpu_id;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     FunctionalMemory *mem;
     AlphaITB *itb;
     AlphaDTB *dtb;
@@ -176,7 +177,7 @@ class ExecContext
     unsigned storeCondFailures;
 
     // constructor: initialize context from given process structure
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 #else
@@ -193,7 +194,7 @@ class ExecContext
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
     int getInstAsid() { return regs.instAsid(); }
@@ -253,7 +254,7 @@ class ExecContext
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -270,7 +271,7 @@ class ExecContext
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
@@ -404,7 +405,7 @@ class ExecContext
         regs.miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     int readIntrFlag() { return regs.intrflag; }
@@ -423,7 +424,7 @@ class ExecContext
 
     void trap(Fault fault);
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     IntReg getSyscallArg(int i)
     {
         return regs.intRegFile[ArgumentReg0 + i];
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 545165b2b..cba57d189 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -44,7 +44,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     AlphaFullCPU(Params &params);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb;
     AlphaDTB *dtb;
 #endif
@@ -52,7 +52,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     void regStats();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     //Note that the interrupt stuff from the base CPU might be somewhat
     //ISA specific (ie NumInterruptLevels).  These functions might not
     //be needed in FullCPU though.
@@ -131,7 +131,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // Most of the full system code and syscall emulation is not yet
     // implemented.  These functions do show what the final interface will
     // look like.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t *getIpr();
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
@@ -149,7 +149,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 #endif
 
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     // Need to change these into regfile calls that directly set a certain
     // register.  Actually, these functions should handle most of this
     // functionality by themselves; should look up the rename and then
@@ -191,7 +191,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     void copyFromXC();
 
   public:
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool palShadowEnabled;
 
     // Not sure this is used anywhere.
@@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -233,7 +233,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 57c567471..3547fb1b5 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -45,7 +45,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
@@ -69,7 +69,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     Param<int> clock;
     Param<int> numThreads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
 SimObjectParam<AlphaITB *> itb;
@@ -162,7 +162,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     INIT_PARAM(clock, "clock speed"),
     INIT_PARAM(numThreads, "number of HW thread contexts"),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     INIT_PARAM(system, "System object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(itb, "Instruction translation buffer"),
@@ -273,7 +273,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
 {
     DerivAlphaFullCPU *cpu;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
 #else
@@ -295,7 +295,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     params.name = getInstanceName();
     params.numberOfThreads = actual_num_threads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     params.system = system;
     params.cpu_id = cpu_id;
     params.itb = itb;
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 146186e2f..2a764740b 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -39,7 +39,7 @@
 #include "cpu/o3/alpha_params.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/isa_traits.hh"
 //#include "arch/alpha/ev5.hh"
@@ -75,7 +75,7 @@ AlphaFullCPU<Impl>::regStats()
     this->commit.regStats();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 
 // Will probably need to know which thread is calling syscall
 // Will need to pass that information in to the DynInst when it is constructed,
@@ -238,7 +238,7 @@ AlphaFullCPU<Impl>::copyFromXC()
     this->funcExeInst = this->xc->func_exe_inst;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 template <class Impl>
 uint64_t *
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 8a9a681d2..bb90bf21a 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     uint64_t readFpcr();
     void setFpcr(uint64_t val);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     Fault hwrei();
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 437b113e4..d1ebb812d 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -95,7 +95,7 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
     this->cpu->setFpcr(val);
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
diff --git a/cpu/o3/alpha_params.hh b/cpu/o3/alpha_params.hh
index 77e6f3649..79b0937e3 100644
--- a/cpu/o3/alpha_params.hh
+++ b/cpu/o3/alpha_params.hh
@@ -49,7 +49,7 @@ class AlphaSimpleParams : public BaseFullCPU::Params
 {
   public:
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb; AlphaDTB *dtb;
 #else
     std::vector<Process *> workload;
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index ac3d83174..dc0986772 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -186,7 +186,7 @@ SimpleCommit<Impl>::commit()
     // in the IPR.  Look at IPR[EXC_ADDR];
     // hwrei() is what resets the PC to the place where instruction execution
     // beings again.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     if (//checkInterrupts &&
         cpu->check_interrupts() &&
         !cpu->inPalMode(readCommitPC())) {
@@ -397,7 +397,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
         if (!head_inst->isNop()) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
             cpu->trap(inst_fault);
 #else // !FULL_SYSTEM
             panic("fault (%d) detected @ PC %08p", inst_fault,
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index b447439c0..adc7b6bbc 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -26,7 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifdef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
 #include "sim/system.hh"
 #else
 #include "sim/process.hh"
@@ -68,7 +70,7 @@ FullO3CPU<Impl>::TickEvent::description()
 //Call constructor to all the pipeline stages here
 template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(Params &params)
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     : BaseFullCPU(params),
 #else
     : BaseFullCPU(params),
@@ -105,7 +107,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       globalSeqNum(1),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
       system(params.system),
       memCtrl(system->memctrl),
       physmem(system->physmem),
@@ -125,12 +127,12 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 {
     _status = Idle;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     thread.resize(this->number_of_threads);
 #endif
 
     for (int i = 0; i < this->number_of_threads; ++i) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         assert(i == 0);
         system->execContexts[i] =
             new ExecContext(this, i, system, itb, dtb, mem);
@@ -153,7 +155,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
     // Note that this is a hack so that my code which still uses xc-> will
     // still work.  I should remove this eventually
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     xc = system->execContexts[0];
 #else
     xc = thread[0];
@@ -246,7 +248,7 @@ FullO3CPU<Impl>::init()
 
         // Need to do a copy of the xc->regs into the CPU's regfile so
         // that it can start properly.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         ExecContext *src_xc = system->execContexts[0];
 #else
         ExecContext *src_xc = thread[0];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 10f60b5da..75dca5056 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -42,13 +42,14 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 using namespace EV5;
 #endif
@@ -62,7 +63,7 @@ class BaseFullCPU : public BaseCPU
   public:
     typedef BaseCPU::Params Params;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     BaseFullCPU(Params &params);
 #else
     BaseFullCPU(Params &params);
@@ -143,7 +144,7 @@ class FullO3CPU : public BaseFullCPU
     /** Get the current instruction sequence number, and increment it. */
     InstSeqNum getAndIncrementInstSeq();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     /** Check if this address is a valid instruction address. */
     bool validInstAddr(Addr addr) { return true; }
 
@@ -325,7 +326,7 @@ class FullO3CPU : public BaseFullCPU
     /** Temporary function to get pointer to exec context. */
     ExecContext *xcBase()
     {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         return system->execContexts[0];
 #else
         return thread[0];
@@ -334,7 +335,7 @@ class FullO3CPU : public BaseFullCPU
 
     InstSeqNum globalSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     MemoryController *memCtrl;
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index 75b6abb3d..c943fd36a 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -80,7 +80,7 @@ SimpleFetch<Impl>::SimpleFetch(Params &params)
     memReq = new MemReq();
     // Not sure of this parameter.  I think it should be based on the
     // thread number.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     memReq->asid = 0;
 #else
     memReq->asid = 0;
@@ -229,7 +229,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
     // of the instructions in the cache line until either the end of the
     // cache line or a predicted taken branch is encountered.
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Flag to say whether or not address is physical addr.
     unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
 #else
@@ -605,7 +605,7 @@ SimpleFetch<Impl>::fetch()
         DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
 
         _status = Blocked;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 //        cpu->trap(fault);
         // Send a signal to the ROB indicating that there's a trap from the
         // fetch stage that needs to be handled.  Need to indicate that
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index 69cd3799a..af23c6f45 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -35,6 +35,7 @@
 
 #include <queue>
 
+#include "config/full_system.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/o3/comm.hh"
@@ -169,7 +170,7 @@ class SimpleIEW
 
     LDSTQ ldstQueue;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
   public:
     void lsqWriteback();
 #endif
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index 5f0d7b647..b8a2b4dc9 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -726,7 +726,7 @@ SimpleIEW<Impl>::iew()
     issueToExecQueue.advance();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 template<class Impl>
 void
 SimpleIEW<Impl>::lsqWriteback()
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index e63b7fcfb..4d47b8f9c 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -33,9 +33,10 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 #include "kern/kernel_stats.hh"
 
@@ -209,7 +210,7 @@ class PhysRegFile
         miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     InternalProcReg *getIpr() { return ipr; }
@@ -235,7 +236,7 @@ class PhysRegFile
     /** Next-cycle program counter. */
     Addr npc;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
     IntReg palregs[NumIntRegs];	// PAL shadow registers
@@ -267,7 +268,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
     memset(floatRegFile, 0, sizeof(*floatRegFile));
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 //Problem:  This code doesn't make sense at the RegFile level because it
 //needs things such as the itb and dtb.  Either put it at the CPU level or
@@ -629,6 +630,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     return No_Fault;
 }
 
-#endif // #ifdef FULL_SYSTEM
+#endif // #if FULL_SYSTEM
 
 #endif // __CPU_O3_CPU_REGFILE_HH__
diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh
index 5fd62e911..2068b36ab 100644
--- a/cpu/o3/rename_impl.hh
+++ b/cpu/o3/rename_impl.hh
@@ -28,6 +28,7 @@
 
 #include <list>
 
+#include "config/full_system.hh"
 #include "cpu/o3/rename.hh"
 
 template <class Impl>
@@ -232,7 +233,7 @@ SimpleRename<Impl>::doSquash()
 
     InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     assert(!historyBuffer.empty());
 #else
     // After a syscall squashes everything, the history buffer may be empty
@@ -543,7 +544,7 @@ SimpleRename<Impl>::tick()
 
     // Ugly code, revamp all of the tick() functions eventually.
     if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (!fromCommit->commitInfo.squash) {
             removeFromHistory(fromCommit->commitInfo.doneSeqNum);
         }
diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh
index 51f4afe75..e7a5671d9 100644
--- a/cpu/o3/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -29,6 +29,7 @@
 #ifndef __CPU_O3_CPU_ROB_IMPL_HH__
 #define __CPU_O3_CPU_ROB_IMPL_HH__
 
+#include "config/full_system.hh"
 #include "cpu/o3/rob.hh"
 
 template <class Impl>
@@ -209,7 +210,7 @@ ROB<Impl>::doSquash()
         // will never be false.  Normally the squash would never be able
         // to go past the head of the ROB; in this case it might, so it
         // must be handled otherwise it will segfault.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (squashIt == cpu->instList.begin()) {
             DPRINTF(ROB, "ROB: Reached head of instruction list while "
                     "squashing.\n");
diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 09702c3f9..5af77862a 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -30,6 +30,7 @@
 #define __CPU_OOO_CPU_OOO_CPU_HH__
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "encumbered/cpu/full/fu_pool.hh"
@@ -40,7 +41,7 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class Processor;
 class AlphaITB;
 class AlphaDTB;
@@ -147,7 +148,7 @@ class OoOCPU : public BaseCPU
         MemInterface *icache_interface;
         MemInterface *dcache_interface;
         int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
         FunctionalMemory *mem;
@@ -173,7 +174,7 @@ class OoOCPU : public BaseCPU
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -279,7 +280,7 @@ class OoOCPU : public BaseCPU
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
     int getInstAsid() { return xc->regs.instAsid(); }
@@ -381,7 +382,7 @@ class OoOCPU : public BaseCPU
     DynInstPtr commitTable[ISA::TotalNumRegs];
 
     // Might need a table of the shadow registers as well.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     DynInstPtr palShadowTable[ISA::NumIntRegs];
 #endif
 
@@ -510,7 +511,7 @@ class OoOCPU : public BaseCPU
     uint64_t readFpcr() { return xc->readFpcr(); }
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
     Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
diff --git a/cpu/pc_event.cc b/cpu/pc_event.cc
index aa6c51466..c3bb3dbe6 100644
--- a/cpu/pc_event.cc
+++ b/cpu/pc_event.cc
@@ -32,6 +32,7 @@
 #include <utility>
 
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
@@ -131,7 +132,7 @@ BreakPCEvent::process(ExecContext *xc)
         delete this;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 extern "C"
 void
 sched_break_pc_sys(System *sys, Addr addr)
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index c5e12990b..1bd5547e7 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -59,7 +59,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
@@ -115,7 +115,7 @@ SimpleCPU::SimpleCPU(Params *p)
       cacheCompletionEvent(this)
 {
     _status = Idle;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
     // initialize CPU, including PC
@@ -562,7 +562,7 @@ SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 }
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 Addr
 SimpleCPU::dbg_vtophys(Addr addr)
 {
@@ -608,7 +608,7 @@ SimpleCPU::processCacheCompletion()
     }
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 void
 SimpleCPU::post_interrupt(int int_num, int index)
 {
@@ -631,7 +631,7 @@ SimpleCPU::tick()
 
     Fault fault = No_Fault;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
         status() != IcacheMissComplete) {
         int ipl = 0;
@@ -692,7 +692,7 @@ SimpleCPU::tick()
         // Try to fetch an instruction
 
         // set up memory request for instruction fetch
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
 #else
 #define IFETCH_FLAGS(pc)	0
@@ -744,7 +744,7 @@ SimpleCPU::tick()
         traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
                                          xc->regs.pc);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         xc->setInst(inst);
 #endif // FULL_SYSTEM
 
@@ -752,7 +752,7 @@ SimpleCPU::tick()
 
         fault = curStaticInst->execute(this, traceData);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         if (xc->fnbin)
             xc->execute(curStaticInst.get());
 #endif
@@ -778,7 +778,7 @@ SimpleCPU::tick()
     }	// if (fault == No_Fault)
 
     if (fault != No_Fault) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         xc->ev5_trap(fault);
 #else // !FULL_SYSTEM
         fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
@@ -790,7 +790,7 @@ SimpleCPU::tick()
         xc->regs.npc += sizeof(MachInst);
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr oldpc;
     do {
         oldpc = xc->regs.pc;
@@ -818,7 +818,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     SimObjectParam<AlphaITB *> itb;
     SimObjectParam<AlphaDTB *> dtb;
     SimObjectParam<FunctionalMemory *> mem;
@@ -850,7 +850,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     INIT_PARAM(itb, "Instruction TLB"),
     INIT_PARAM(dtb, "Data TLB"),
     INIT_PARAM(mem, "memory"),
@@ -888,7 +888,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
     params->width = width;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     params->itb = itb;
     params->dtb = dtb;
     params->mem = mem;
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index e8394db3f..0f7251237 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -30,6 +30,7 @@
 #define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
 
 #include "base/statistics.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/pc_event.hh"
@@ -38,7 +39,7 @@
 #include "sim/eventq.hh"
 
 // forward declarations
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 class Processor;
 class AlphaITB;
 class AlphaDTB;
@@ -130,7 +131,7 @@ class SimpleCPU : public BaseCPU
         MemInterface *icache_interface;
         MemInterface *dcache_interface;
         int width;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         AlphaITB *itb;
         AlphaDTB *dtb;
         FunctionalMemory *mem;
@@ -148,7 +149,7 @@ class SimpleCPU : public BaseCPU
     void switchOut(Sampler *s);
     void takeOverFrom(BaseCPU *oldCPU);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     Addr dbg_vtophys(Addr addr);
 
     bool interval_stats;
@@ -323,7 +324,7 @@ class SimpleCPU : public BaseCPU
     uint64_t readFpcr() { return xc->readFpcr(); }
     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
     Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
author	Steve Reinhardt <stever@eecs.umich.edu>	2005-08-30 13:18:54 -0400
committer	Steve Reinhardt <stever@eecs.umich.edu>	2005-08-30 13:18:54 -0400
commit	c4793184bd32e97e8932a9a0355d8a7b8a214752 (patch)
tree	d616bdd39c608898bd5fea6928166175e96d8d79 /cpu
parent	e007aa59e3da2609de92cc6d2cfcd7acf9d4276f (diff)
download	gem5-c4793184bd32e97e8932a9a0355d8a7b8a214752.tar.xz