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authorRon Dreslinski <rdreslin@umich.edu>2004-11-14 16:19:11 -0500
committerRon Dreslinski <rdreslin@umich.edu>2004-11-14 16:19:11 -0500
commitf7d1166e04aa3ec2d13df382832edb5157118410 (patch)
treecf15d02622ee384e18a7327bbacd8bd0afe5afa5 /cpu
parentcf5eea0e456011d2c2dba28b75497fb6980ae364 (diff)
parenta89398e26271ce8e299aa77b521591c363a492ab (diff)
downloadgem5-f7d1166e04aa3ec2d13df382832edb5157118410.tar.xz
Merge zizzer:/z/m5/Bitkeeper/m5
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/clean --HG-- extra : convert_revision : 170f5fd8891b02ad3cc04112c6f304ede3254dae
Diffstat (limited to 'cpu')
-rw-r--r--cpu/exec_context.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 2ba2d7524..8437a5585 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -196,8 +196,8 @@ class ExecContext
#ifdef FULL_SYSTEM
bool validInstAddr(Addr addr) { return true; }
bool validDataAddr(Addr addr) { return true; }
- int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
- int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
+ int getInstAsid() { return regs.instAsid(); }
+ int getDataAsid() { return regs.dataAsid(); }
Fault translateInstReq(MemReqPtr &req)
{
@@ -410,7 +410,7 @@ class ExecContext
int readIntrFlag() { return regs.intrflag; }
void setIntrFlag(int val) { regs.intrflag = val; }
Fault hwrei();
- bool inPalMode() { return PC_PAL(regs.pc); }
+ bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
void ev5_trap(Fault fault);
bool simPalCheck(int palFunc);
#endif