Add opt cpu and fix page copy warnings

SConscript:
    Add opt_cpu
cpu/simple_cpu/simple_cpu.cc:
    Fix page spanning copy warning.
cpu/trace/reader/itx_reader.cc:
    Fix reader to return correct address.

--HG--
extra : convert_revision : f03e244971af4197743c7c717d64f21db0ae42d3

4 files changed, 436 insertions, 6 deletions

diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 18e660483..0b45d2b9d 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -345,8 +345,9 @@ SimpleCPU::copySrcTranslate(Addr src)
     int offset = src & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (src & (~8191)) == ((src + blk_size) & (~8191))) {
-        warn("Copied block source spans pages.");
+    if (no_warn && (src & (~8191)) != ((src + blk_size) & (~8191)) &&
+        (src >> 40) != 0xfffffc) {
+        warn("Copied block source spans pages %x.", src);
         no_warn = false;
     }
 
@@ -380,9 +381,10 @@ SimpleCPU::copy(Addr dest)
     int offset = dest & (blk_size - 1);
 
     // Make sure block doesn't span page
-    if (no_warn && (dest & (~8191)) == ((dest + blk_size) & (~8191))) {
+    if (no_warn && (dest & (~8191)) != ((dest + blk_size) & (~8191)) &&
+        (dest >> 40) != 0xfffffc) {
         no_warn = false;
-        warn("Copied block destination spans pages. ");
+        warn("Copied block destination spans pages %x. ", dest);
     }
 
     memReq->reset(dest & ~(blk_size -1), blk_size);
diff --git a/cpu/trace/opt_cpu.cc b/cpu/trace/opt_cpu.cc
new file mode 100644
index 000000000..c23b72856
--- /dev/null
+++ b/cpu/trace/opt_cpu.cc
@@ -0,0 +1,210 @@
+
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Definition of a memory trace CPU object for optimal caches. Uses a memory
+ * trace to access a fully associative cache with optimal replacement.
+ */
+
+#include <algorithm> // For heap functions.
+
+#include "cpu/trace/opt_cpu.hh"
+#include "cpu/trace/reader/mem_trace_reader.hh"
+
+#include "sim/builder.hh"
+#include "sim/sim_events.hh"
+
+using namespace std;
+
+OptCPU::OptCPU(const string &name,
+              MemTraceReader *_trace,
+              int log_block_size,
+              int cache_size)
+    : BaseCPU(name,1), tickEvent(this), trace(_trace),
+      numBlks(cache_size/(1<<log_block_size))
+{
+    MemReqPtr req;
+    trace->getNextReq(req);
+    assert(log_block_size >= 4);
+    assert(refInfo.size() == 0);
+    while (req && (refInfo.size() < 60000000)) {
+        RefInfo temp;
+        temp.addr = req->paddr >> log_block_size;
+        refInfo.push_back(temp);
+        trace->getNextReq(req);
+    }
+    // Can't handle more references than "infinity"
+    assert(refInfo.size() < InfiniteRef);
+
+    // Initialize top level of lookup table.
+    lookupTable.resize(16);
+
+    // Annotate references with next ref time.
+    for (RefIndex i = refInfo.size() - 1; i >= 0; --i) {
+        Addr addr = refInfo[i].addr;
+        initTable(addr, InfiniteRef);
+        refInfo[i].nextRefTime = lookupValue(addr);
+        setValue(addr, i);
+    }
+
+    // Reset the lookup table
+    for (int j = 0; j < 16; ++j) {
+        if (lookupTable[j].size() == (1<<16)) {
+            for (int k = 0; k < (1<<16); ++k) {
+                if (lookupTable[j][k].size() == (1<<16)) {
+                    for (int l = 0; l < (1<<16); ++l) {
+                        lookupTable[j][k][l] = -1;
+                    }
+                }
+            }
+        }
+    }
+
+
+    cacheHeap.resize(numBlks);
+
+    tickEvent.schedule(0);
+
+    hits = 0;
+    misses = 0;
+}
+
+void
+OptCPU::tick()
+{
+    // Do opt simulation
+
+    // Initialize cache
+    int blks_in_cache = 0;
+    RefIndex i = 0;
+
+    while (blks_in_cache < numBlks) {
+        RefIndex cache_index = lookupValue(refInfo[i].addr);
+        if (cache_index == -1) {
+            // First reference to this block
+            misses++;
+            cache_index = blks_in_cache++;
+            setValue(refInfo[i].addr, cache_index);
+        } else {
+            hits++;
+        }
+        // update cache heap to most recent reference
+        cacheHeap[cache_index] = i;
+        if (++i >= refInfo.size()) {
+            // exit
+        }
+    }
+    for (int start = numBlks/2; start >= 0; --start) {
+        heapify(start);
+    }
+    //verifyHeap(0);
+
+    for (; i < refInfo.size(); ++i) {
+        RefIndex cache_index = lookupValue(refInfo[i].addr);
+        if (cache_index == -1) {
+            // miss
+            misses++;
+            // replace from cacheHeap[0]
+            // mark replaced block as absent
+            setValue(refInfo[cacheHeap[0]].addr, -1);
+            cacheHeap[0] = i;
+            heapify(0);
+        } else {
+            // hit
+            hits++;
+            assert(refInfo[cacheHeap[cache_index]].addr == refInfo[i].addr);
+            assert(refInfo[cacheHeap[cache_index]].nextRefTime == i);
+            assert(heapLeft(cache_index) >= numBlks);
+        }
+        cacheHeap[cache_index] = i;
+        processRankIncrease(cache_index);
+    }
+    // exit;
+    fprintf(stderr, "%d, %d, %d\n", misses, hits, refInfo.size());
+    new SimExitEvent("Finshed Memory Trace");
+}
+
+void
+OptCPU::initTable(Addr addr, RefIndex index)
+{
+    int l1_index = (addr >> 32) & 0x0f;
+    int l2_index = (addr >> 16) & 0xffff;
+    assert(l1_index == addr >> 32);
+    if (lookupTable[l1_index].size() != (1<<16)) {
+        lookupTable[l1_index].resize(1<<16);
+    }
+    if (lookupTable[l1_index][l2_index].size() != (1<<16)) {
+        lookupTable[l1_index][l2_index].resize(1<<16, index);
+    }
+}
+
+OptCPU::TickEvent::TickEvent(OptCPU *c)
+    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
+{
+}
+
+void
+OptCPU::TickEvent::process()
+{
+    cpu->tick();
+}
+
+const char *
+OptCPU::TickEvent::description()
+{
+    return "OptCPU tick event";
+}
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
+
+    SimObjectParam<MemTraceReader *> trace;
+    Param<int> size;
+    Param<int> log_block_size;
+
+END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
+
+    INIT_PARAM_DFLT(trace, "instruction cache", NULL),
+    INIT_PARAM(size, "cache size"),
+    INIT_PARAM(log_block_size, "log base 2 of block size")
+
+END_INIT_SIM_OBJECT_PARAMS(OptCPU)
+
+CREATE_SIM_OBJECT(OptCPU)
+{
+    return new OptCPU(getInstanceName(),
+                      trace,
+                      log_block_size,
+                      size);
+}
+
+REGISTER_SIM_OBJECT("OptCPU", OptCPU)
diff --git a/cpu/trace/opt_cpu.hh b/cpu/trace/opt_cpu.hh
new file mode 100644
index 000000000..e366c2068
--- /dev/null
+++ b/cpu/trace/opt_cpu.hh
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2004 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of a memory trace CPU object for optimal caches. Uses a memory
+ * trace to access a fully associative cache with optimal replacement.
+ */
+
+#ifndef __OPT_CPU_HH__
+#define __OPT_CPU_HH__
+
+#include <vector>
+
+#include "cpu/base_cpu.hh"
+#include "mem/mem_req.hh" // for MemReqPtr
+#include "sim/eventq.hh" // for Event
+
+// Forward Declaration
+class MemTraceReader;
+
+/**
+ * A CPU object to simulate a fully-associative cache with optimal replacement.
+ */
+class OptCPU : public BaseCPU
+{
+    typedef int RefIndex;
+
+    typedef std::vector<RefIndex> L3Table;
+    typedef std::vector<L3Table> L2Table;
+    typedef std::vector<L2Table> L1Table;
+
+    /**
+     * Event to call OptCPU::tick
+     */
+    class TickEvent : public Event
+    {
+      private:
+        /** The associated CPU */
+        OptCPU *cpu;
+
+      public:
+        /**
+         * Construct this event;
+         */
+        TickEvent(OptCPU *c);
+
+        /**
+         * Call the tick function.
+         */
+        void process();
+
+        /**
+         * Return a string description of this event.
+         */
+        const char *description();
+    };
+
+    TickEvent tickEvent;
+
+    class RefInfo
+    {
+      public:
+        RefIndex nextRefTime;
+        Addr addr;
+    };
+
+    /** Reference Information. */
+    std::vector<RefInfo> refInfo;
+
+    /** Lookup table to track blocks in the cache heap */
+    L1Table lookupTable;
+
+    /**
+     * Return the correct value in the lookup table.
+     */
+    RefIndex lookupValue(Addr addr)
+    {
+        int l1_index = (addr >> 32) & 0x0f;
+        int l2_index = (addr >> 16) & 0xffff;
+        int l3_index = addr & 0xffff;
+        assert(l1_index == addr >> 32);
+        return lookupTable[l1_index][l2_index][l3_index];
+    }
+
+    /**
+     * Set the value in the lookup table.
+     */
+    void setValue(Addr addr, RefIndex index)
+    {
+        int l1_index = (addr >> 32) & 0x0f;
+        int l2_index = (addr >> 16) & 0xffff;
+        int l3_index = addr & 0xffff;
+        assert(l1_index == addr >> 32);
+        lookupTable[l1_index][l2_index][l3_index]=index;
+    }
+
+    /**
+     * Initialize the lookup table to the given value.
+     */
+    void initTable(Addr addr, RefIndex index);
+
+    void heapSwap(int a, int b) {
+        RefIndex tmp = cacheHeap[a];
+        cacheHeap[a] = cacheHeap[b];
+        cacheHeap[b] = tmp;
+
+        setValue(refInfo[cacheHeap[a]].addr, a);
+        setValue(refInfo[cacheHeap[b]].addr, b);
+    }
+
+    int heapLeft(int index) { return index + index + 1; }
+    int heapRight(int index) { return index + index + 2; }
+    int heapParent(int index) { return (index - 1) >> 1; }
+
+    RefIndex heapRank(int index) {
+        return refInfo[cacheHeap[index]].nextRefTime;
+    }
+
+    void heapify(int start){
+        int left = heapLeft(start);
+        int right = heapRight(start);
+        int max = start;
+        if (left < numBlks && heapRank(left) > heapRank(start)) {
+            max = left;
+        }
+        if (right < numBlks && heapRank(right) >  heapRank(max)) {
+            max = right;
+        }
+
+        if (max != start) {
+            heapSwap(start, max);
+            heapify(max);
+        }
+    }
+
+    void verifyHeap(int start) {
+        int left = heapLeft(start);
+        int right = heapRight(start);
+
+        if (left < numBlks) {
+            assert(heapRank(start) >= heapRank(left));
+            verifyHeap(left);
+        }
+        if (right < numBlks) {
+            assert(heapRank(start) >= heapRank(right));
+            verifyHeap(right);
+        }
+    }
+
+    void processRankIncrease(int start) {
+        int parent = heapParent(start);
+        while (start > 0 && heapRank(parent) < heapRank(start)) {
+            heapSwap(parent, start);
+            start = parent;
+            parent = heapParent(start);
+        }
+    }
+
+    static const RefIndex InfiniteRef = 0x7fffffff;
+
+    /** Memory reference trace. */
+    MemTraceReader *trace;
+
+    /** Cache heap for replacement. */
+    std::vector<RefIndex> cacheHeap;
+
+    /** The number of blocks in the cache. */
+    const int numBlks;
+
+
+    int misses;
+    int hits;
+
+  public:
+    /**
+     * Construct a OptCPU object.
+     */
+    OptCPU(const std::string &name,
+           MemTraceReader *_trace,
+           int log_block_size,
+           int cache_size);
+
+    /**
+     * Perform the optimal replacement simulation.
+     */
+    void tick();
+};
+
+#endif
diff --git a/cpu/trace/reader/itx_reader.cc b/cpu/trace/reader/itx_reader.cc
index 615eb414e..56f06c870 100644
--- a/cpu/trace/reader/itx_reader.cc
+++ b/cpu/trace/reader/itx_reader.cc
@@ -102,6 +102,7 @@ ITXReader::getNextReq(MemReqPtr &req)
                     } else {
                         codePhysAddr += tmp_req->size;
                     }
+                    assert(tmp_req->paddr >> 36 == 0);
                 } else {
                     codePhysValid = false;
                 }
@@ -130,13 +131,13 @@ ITXReader::getNextReq(MemReqPtr &req)
                     // Get the page offset from the virtual address.
                     tmp_req->paddr = tmp_req->vaddr & 0xfff;
                     tmp_req->paddr |= (c & 0xf0) << 8;
-                    tmp_req->paddr |= (Addr)(c & 0xf0) << 32;
+                    tmp_req->paddr |= (Addr)(c & 0x0f) << 32;
                     for (int i = 2; i < 4; ++i) {
                         c = getc(trace);
                         if (c == EOF) {
                             fatal("Unexpected end of trace file.");
                         }
-                        tmp_req->paddr |= (c & 0xff) << (8 * i);
+                        tmp_req->paddr |= (Addr)(c & 0xff) << (8 * i);
                     }
                     if (type == ITXCode) {
                         if (((tmp_req->paddr & 0xfff) + tmp_req->size)
@@ -149,6 +150,7 @@ ITXReader::getNextReq(MemReqPtr &req)
                             codePhysValid = true;
                         }
                     }
+                    assert(tmp_req->paddr >> 36 == 0);
                 } else if (type == ITXCode) {
                     codePhysValid = false;
                 }
@@ -175,6 +177,7 @@ ITXReader::getNextReq(MemReqPtr &req)
         }
     } while (!phys_val);
     req = tmp_req;
+    assert(!req || (req->paddr >> 36) == 0);
     return 0;
 }