Changes for getting FreeBSD to run.

SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780

4 files changed, 6 insertions, 6 deletions

diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index e9ff3e181..5e105c44d 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -263,7 +263,7 @@ class ExecContext
 
         Fault error;
         error = mem->read(req, data);
-        data = htoa(data);
+        data = gtoh(data);
         return error;
     }
 
@@ -313,7 +313,7 @@ class ExecContext
         }
 
 #endif
-        return mem->write(req, (T)htoa(data));
+        return mem->write(req, (T)htog(data));
     }
 
     virtual bool misspeculating();
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 3c679c3b2..545165b2b 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -220,7 +220,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
         Fault error;
         error = this->mem->read(req, data);
-        data = htoa(data);
+        data = gtoh(data);
         return error;
     }
 
@@ -277,7 +277,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 
 #endif
 
-        return this->mem->write(req, (T)htoa(data));
+        return this->mem->write(req, (T)htog(data));
     }
 
     template <class T>
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index 83d7a02e5..75b6abb3d 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -535,7 +535,7 @@ SimpleFetch<Impl>::fetch()
             assert(offset <= cacheBlkSize - instSize);
 
             // Get the instruction from the array of the cache line.
-            inst = htoa(*reinterpret_cast<MachInst *>
+            inst = gtoh(*reinterpret_cast<MachInst *>
                         (&cacheData[offset]));
 
             // Create a new DynInst from the instruction fetched.
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 1164e35a4..c5e12990b 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -738,7 +738,7 @@ SimpleCPU::tick()
         comInstEventQueue[0]->serviceEvents(numInst);
 
         // decode the instruction
-        inst = htoa(inst);
+        inst = gtoh(inst);
         curStaticInst = StaticInst<TheISA>::decode(inst);
 
         traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,